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[RISCV] Implement getIPRACSRegs hook #125586

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Merged
merged 3 commits into from
Feb 4, 2025
Merged

[RISCV] Implement getIPRACSRegs hook #125586

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0f80bdf
Implement getIPRACSRegs hook for riscv
mikhailramalho Feb 3, 2025
c3f5c8f
Update test
mikhailramalho Feb 3, 2025
873a337
Removed comment
mikhailramalho Feb 3, 2025
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2 changes: 2 additions & 0 deletions llvm/lib/Target/RISCV/RISCVCallingConv.td
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Expand Up @@ -42,6 +42,8 @@ def CSR_ILP32D_LP64D_V
// Needed for implementation of RISCVRegisterInfo::getNoPreservedMask()
def CSR_NoRegs : CalleeSavedRegs<(add)>;

def CSR_IPRA : CalleeSavedRegs<(add X1)>;

// Interrupt handler needs to save/restore all registers that are used,
// both Caller and Callee saved registers.
def CSR_Interrupt : CalleeSavedRegs<(add X1, (sequence "X%u", 5, 31))>;
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5 changes: 5 additions & 0 deletions llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
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Expand Up @@ -55,6 +55,11 @@ RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
: RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
/*PC*/0, HwMode) {}

const MCPhysReg *
RISCVRegisterInfo::getIPRACSRegs(const MachineFunction *MF) const {
return CSR_IPRA_SaveList;
}

const MCPhysReg *
RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
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2 changes: 2 additions & 0 deletions llvm/lib/Target/RISCV/RISCVRegisterInfo.h
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Expand Up @@ -62,6 +62,8 @@ struct RISCVRegisterInfo : public RISCVGenRegisterInfo {

const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;

const MCPhysReg *getIPRACSRegs(const MachineFunction *MF) const override;

BitVector getReservedRegs(const MachineFunction &MF) const override;
bool isAsmClobberable(const MachineFunction &MF,
MCRegister PhysReg) const override;
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17 changes: 10 additions & 7 deletions llvm/test/CodeGen/RISCV/ipra.ll
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Expand Up @@ -63,26 +63,29 @@ entry:
ret i32 0
}

; FIXME: this function calls another function but doesn't save/restore ra
define internal void @foobar(ptr %live_throughout.0.val) norecurse nounwind {
; RV64-LABEL: foobar:
; RV64: # %bb.0: # %entry
; RV64-NEXT: addi sp, sp, -48
; RV64-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64-NEXT: mv a1, a0
; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: addi a2, sp, 12
; RV64-NEXT: addi a0, sp, 8
; RV64-NEXT: addi a2, sp, 4
; RV64-NEXT: call bmp_iter_set_init
; RV64-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 48
; RV64-NEXT: ret
;
; RV32-LABEL: foobar:
; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -32
; RV32-NEXT: addi sp, sp, -48
; RV32-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32-NEXT: mv a1, a0
; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: addi a2, sp, 4
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: addi a2, sp, 12
; RV32-NEXT: call bmp_iter_set_init
; RV32-NEXT: addi sp, sp, 32
; RV32-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 48
; RV32-NEXT: ret
;
; RV64-WITHFP-LABEL: foobar:
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