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[X86] LowerSelect - use BLENDV for scalar selection on all SSE41+ targets #125853

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Feb 10, 2025
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[X86] LowerSelect - use BLENDV for scalar selection on all SSE41+ targets #125853

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5e164e0
[X86] LowerSelect - use BLENDV for scalar selection if not all operan…
RKSimon Feb 5, 2025
f56c768
[TEST] Drop SSE41 constraints
RKSimon Feb 5, 2025
63a85a1
Merge branch 'upstream' into sse41-scalar-blendv
RKSimon Feb 10, 2025
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13 changes: 4 additions & 9 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -24648,19 +24648,14 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,
DAG.getTargetConstant(SSECC, DL, MVT::i8));

// If we have AVX, we can use a variable vector select (VBLENDV) instead
// of 3 logic instructions for size savings and potentially speed.
// If we have SSE41/AVX, we can use a variable vector select (VBLENDV)
// instead of 3 logic instructions for size savings and potentially speed.
// Unfortunately, there is no scalar form of VBLENDV.

//
// If either operand is a +0.0 constant, don't try this. We can expect to
// optimize away at least one of the logic instructions later in that
// case, so that sequence would be faster than a variable blend.

// BLENDV was introduced with SSE 4.1, but the 2 register form implicitly
// uses XMM0 as the selection register. That may need just as many
// instructions as the AND/ANDN/OR sequence due to register moves, so
// don't bother.
if (Subtarget.hasAVX() && !isNullFPConstant(Op1) &&
if (Subtarget.hasSSE41() && !isNullFPConstant(Op1) &&
!isNullFPConstant(Op2)) {
// Convert to vectors, do a VSELECT, and convert back to scalar.
// All of the conversions should be optimized away.
Expand Down
124 changes: 80 additions & 44 deletions llvm/test/CodeGen/X86/fmaxnum.ll
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Expand Up @@ -22,17 +22,26 @@ declare <8 x double> @llvm.maxnum.v8f64(<8 x double>, <8 x double>)
; FIXME: As the vector tests show, the SSE run shouldn't need this many moves.

define float @test_fmaxf(float %x, float %y) {
; SSE-LABEL: test_fmaxf:
; SSE: # %bb.0:
; SSE-NEXT: movaps %xmm0, %xmm2
; SSE-NEXT: cmpunordss %xmm0, %xmm2
; SSE-NEXT: movaps %xmm2, %xmm3
; SSE-NEXT: andps %xmm1, %xmm3
; SSE-NEXT: maxss %xmm0, %xmm1
; SSE-NEXT: andnps %xmm1, %xmm2
; SSE-NEXT: orps %xmm3, %xmm2
; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: retq
; SSE2-LABEL: test_fmaxf:
; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm2
; SSE2-NEXT: cmpunordss %xmm0, %xmm2
; SSE2-NEXT: movaps %xmm2, %xmm3
; SSE2-NEXT: andps %xmm1, %xmm3
; SSE2-NEXT: maxss %xmm0, %xmm1
; SSE2-NEXT: andnps %xmm1, %xmm2
; SSE2-NEXT: orps %xmm3, %xmm2
; SSE2-NEXT: movaps %xmm2, %xmm0
; SSE2-NEXT: retq
;
; SSE4-LABEL: test_fmaxf:
; SSE4: # %bb.0:
; SSE4-NEXT: movaps %xmm1, %xmm2
; SSE4-NEXT: maxss %xmm0, %xmm2
; SSE4-NEXT: cmpunordss %xmm0, %xmm0
; SSE4-NEXT: blendvps %xmm0, %xmm1, %xmm2
; SSE4-NEXT: movaps %xmm2, %xmm0
; SSE4-NEXT: retq
;
; AVX1-LABEL: test_fmaxf:
; AVX1: # %bb.0:
Expand Down Expand Up @@ -63,17 +72,26 @@ define float @test_fmaxf_minsize(float %x, float %y) minsize {
; FIXME: As the vector tests show, the SSE run shouldn't need this many moves.

define double @test_fmax(double %x, double %y) {
; SSE-LABEL: test_fmax:
; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm0, %xmm2
; SSE-NEXT: cmpunordsd %xmm0, %xmm2
; SSE-NEXT: movapd %xmm2, %xmm3
; SSE-NEXT: andpd %xmm1, %xmm3
; SSE-NEXT: maxsd %xmm0, %xmm1
; SSE-NEXT: andnpd %xmm1, %xmm2
; SSE-NEXT: orpd %xmm3, %xmm2
; SSE-NEXT: movapd %xmm2, %xmm0
; SSE-NEXT: retq
; SSE2-LABEL: test_fmax:
; SSE2: # %bb.0:
; SSE2-NEXT: movapd %xmm0, %xmm2
; SSE2-NEXT: cmpunordsd %xmm0, %xmm2
; SSE2-NEXT: movapd %xmm2, %xmm3
; SSE2-NEXT: andpd %xmm1, %xmm3
; SSE2-NEXT: maxsd %xmm0, %xmm1
; SSE2-NEXT: andnpd %xmm1, %xmm2
; SSE2-NEXT: orpd %xmm3, %xmm2
; SSE2-NEXT: movapd %xmm2, %xmm0
; SSE2-NEXT: retq
;
; SSE4-LABEL: test_fmax:
; SSE4: # %bb.0:
; SSE4-NEXT: movapd %xmm1, %xmm2
; SSE4-NEXT: maxsd %xmm0, %xmm2
; SSE4-NEXT: cmpunordsd %xmm0, %xmm0
; SSE4-NEXT: blendvpd %xmm0, %xmm1, %xmm2
; SSE4-NEXT: movapd %xmm2, %xmm0
; SSE4-NEXT: retq
;
; AVX1-LABEL: test_fmax:
; AVX1: # %bb.0:
Expand Down Expand Up @@ -111,17 +129,26 @@ define x86_fp80 @test_fmaxl(x86_fp80 %x, x86_fp80 %y) {
}

define float @test_intrinsic_fmaxf(float %x, float %y) {
; SSE-LABEL: test_intrinsic_fmaxf:
; SSE: # %bb.0:
; SSE-NEXT: movaps %xmm0, %xmm2
; SSE-NEXT: cmpunordss %xmm0, %xmm2
; SSE-NEXT: movaps %xmm2, %xmm3
; SSE-NEXT: andps %xmm1, %xmm3
; SSE-NEXT: maxss %xmm0, %xmm1
; SSE-NEXT: andnps %xmm1, %xmm2
; SSE-NEXT: orps %xmm3, %xmm2
; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: retq
; SSE2-LABEL: test_intrinsic_fmaxf:
; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm2
; SSE2-NEXT: cmpunordss %xmm0, %xmm2
; SSE2-NEXT: movaps %xmm2, %xmm3
; SSE2-NEXT: andps %xmm1, %xmm3
; SSE2-NEXT: maxss %xmm0, %xmm1
; SSE2-NEXT: andnps %xmm1, %xmm2
; SSE2-NEXT: orps %xmm3, %xmm2
; SSE2-NEXT: movaps %xmm2, %xmm0
; SSE2-NEXT: retq
;
; SSE4-LABEL: test_intrinsic_fmaxf:
; SSE4: # %bb.0:
; SSE4-NEXT: movaps %xmm1, %xmm2
; SSE4-NEXT: maxss %xmm0, %xmm2
; SSE4-NEXT: cmpunordss %xmm0, %xmm0
; SSE4-NEXT: blendvps %xmm0, %xmm1, %xmm2
; SSE4-NEXT: movaps %xmm2, %xmm0
; SSE4-NEXT: retq
;
; AVX1-LABEL: test_intrinsic_fmaxf:
; AVX1: # %bb.0:
Expand All @@ -142,17 +169,26 @@ define float @test_intrinsic_fmaxf(float %x, float %y) {
}

define double @test_intrinsic_fmax(double %x, double %y) {
; SSE-LABEL: test_intrinsic_fmax:
; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm0, %xmm2
; SSE-NEXT: cmpunordsd %xmm0, %xmm2
; SSE-NEXT: movapd %xmm2, %xmm3
; SSE-NEXT: andpd %xmm1, %xmm3
; SSE-NEXT: maxsd %xmm0, %xmm1
; SSE-NEXT: andnpd %xmm1, %xmm2
; SSE-NEXT: orpd %xmm3, %xmm2
; SSE-NEXT: movapd %xmm2, %xmm0
; SSE-NEXT: retq
; SSE2-LABEL: test_intrinsic_fmax:
; SSE2: # %bb.0:
; SSE2-NEXT: movapd %xmm0, %xmm2
; SSE2-NEXT: cmpunordsd %xmm0, %xmm2
; SSE2-NEXT: movapd %xmm2, %xmm3
; SSE2-NEXT: andpd %xmm1, %xmm3
; SSE2-NEXT: maxsd %xmm0, %xmm1
; SSE2-NEXT: andnpd %xmm1, %xmm2
; SSE2-NEXT: orpd %xmm3, %xmm2
; SSE2-NEXT: movapd %xmm2, %xmm0
; SSE2-NEXT: retq
;
; SSE4-LABEL: test_intrinsic_fmax:
; SSE4: # %bb.0:
; SSE4-NEXT: movapd %xmm1, %xmm2
; SSE4-NEXT: maxsd %xmm0, %xmm2
; SSE4-NEXT: cmpunordsd %xmm0, %xmm0
; SSE4-NEXT: blendvpd %xmm0, %xmm1, %xmm2
; SSE4-NEXT: movapd %xmm2, %xmm0
; SSE4-NEXT: retq
;
; AVX1-LABEL: test_intrinsic_fmax:
; AVX1: # %bb.0:
Expand Down
124 changes: 80 additions & 44 deletions llvm/test/CodeGen/X86/fminnum.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -22,17 +22,26 @@ declare <8 x double> @llvm.minnum.v8f64(<8 x double>, <8 x double>)
; FIXME: As the vector tests show, the SSE run shouldn't need this many moves.

define float @test_fminf(float %x, float %y) {
; SSE-LABEL: test_fminf:
; SSE: # %bb.0:
; SSE-NEXT: movaps %xmm0, %xmm2
; SSE-NEXT: cmpunordss %xmm0, %xmm2
; SSE-NEXT: movaps %xmm2, %xmm3
; SSE-NEXT: andps %xmm1, %xmm3
; SSE-NEXT: minss %xmm0, %xmm1
; SSE-NEXT: andnps %xmm1, %xmm2
; SSE-NEXT: orps %xmm3, %xmm2
; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: retq
; SSE2-LABEL: test_fminf:
; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm2
; SSE2-NEXT: cmpunordss %xmm0, %xmm2
; SSE2-NEXT: movaps %xmm2, %xmm3
; SSE2-NEXT: andps %xmm1, %xmm3
; SSE2-NEXT: minss %xmm0, %xmm1
; SSE2-NEXT: andnps %xmm1, %xmm2
; SSE2-NEXT: orps %xmm3, %xmm2
; SSE2-NEXT: movaps %xmm2, %xmm0
; SSE2-NEXT: retq
;
; SSE4-LABEL: test_fminf:
; SSE4: # %bb.0:
; SSE4-NEXT: movaps %xmm1, %xmm2
; SSE4-NEXT: minss %xmm0, %xmm2
; SSE4-NEXT: cmpunordss %xmm0, %xmm0
; SSE4-NEXT: blendvps %xmm0, %xmm1, %xmm2
; SSE4-NEXT: movaps %xmm2, %xmm0
; SSE4-NEXT: retq
;
; AVX1-LABEL: test_fminf:
; AVX1: # %bb.0:
Expand Down Expand Up @@ -63,17 +72,26 @@ define float @test_fminf_minsize(float %x, float %y) minsize {
; FIXME: As the vector tests show, the SSE run shouldn't need this many moves.

define double @test_fmin(double %x, double %y) {
; SSE-LABEL: test_fmin:
; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm0, %xmm2
; SSE-NEXT: cmpunordsd %xmm0, %xmm2
; SSE-NEXT: movapd %xmm2, %xmm3
; SSE-NEXT: andpd %xmm1, %xmm3
; SSE-NEXT: minsd %xmm0, %xmm1
; SSE-NEXT: andnpd %xmm1, %xmm2
; SSE-NEXT: orpd %xmm3, %xmm2
; SSE-NEXT: movapd %xmm2, %xmm0
; SSE-NEXT: retq
; SSE2-LABEL: test_fmin:
; SSE2: # %bb.0:
; SSE2-NEXT: movapd %xmm0, %xmm2
; SSE2-NEXT: cmpunordsd %xmm0, %xmm2
; SSE2-NEXT: movapd %xmm2, %xmm3
; SSE2-NEXT: andpd %xmm1, %xmm3
; SSE2-NEXT: minsd %xmm0, %xmm1
; SSE2-NEXT: andnpd %xmm1, %xmm2
; SSE2-NEXT: orpd %xmm3, %xmm2
; SSE2-NEXT: movapd %xmm2, %xmm0
; SSE2-NEXT: retq
;
; SSE4-LABEL: test_fmin:
; SSE4: # %bb.0:
; SSE4-NEXT: movapd %xmm1, %xmm2
; SSE4-NEXT: minsd %xmm0, %xmm2
; SSE4-NEXT: cmpunordsd %xmm0, %xmm0
; SSE4-NEXT: blendvpd %xmm0, %xmm1, %xmm2
; SSE4-NEXT: movapd %xmm2, %xmm0
; SSE4-NEXT: retq
;
; AVX1-LABEL: test_fmin:
; AVX1: # %bb.0:
Expand Down Expand Up @@ -111,17 +129,26 @@ define x86_fp80 @test_fminl(x86_fp80 %x, x86_fp80 %y) {
}

define float @test_intrinsic_fminf(float %x, float %y) {
; SSE-LABEL: test_intrinsic_fminf:
; SSE: # %bb.0:
; SSE-NEXT: movaps %xmm0, %xmm2
; SSE-NEXT: cmpunordss %xmm0, %xmm2
; SSE-NEXT: movaps %xmm2, %xmm3
; SSE-NEXT: andps %xmm1, %xmm3
; SSE-NEXT: minss %xmm0, %xmm1
; SSE-NEXT: andnps %xmm1, %xmm2
; SSE-NEXT: orps %xmm3, %xmm2
; SSE-NEXT: movaps %xmm2, %xmm0
; SSE-NEXT: retq
; SSE2-LABEL: test_intrinsic_fminf:
; SSE2: # %bb.0:
; SSE2-NEXT: movaps %xmm0, %xmm2
; SSE2-NEXT: cmpunordss %xmm0, %xmm2
; SSE2-NEXT: movaps %xmm2, %xmm3
; SSE2-NEXT: andps %xmm1, %xmm3
; SSE2-NEXT: minss %xmm0, %xmm1
; SSE2-NEXT: andnps %xmm1, %xmm2
; SSE2-NEXT: orps %xmm3, %xmm2
; SSE2-NEXT: movaps %xmm2, %xmm0
; SSE2-NEXT: retq
;
; SSE4-LABEL: test_intrinsic_fminf:
; SSE4: # %bb.0:
; SSE4-NEXT: movaps %xmm1, %xmm2
; SSE4-NEXT: minss %xmm0, %xmm2
; SSE4-NEXT: cmpunordss %xmm0, %xmm0
; SSE4-NEXT: blendvps %xmm0, %xmm1, %xmm2
; SSE4-NEXT: movaps %xmm2, %xmm0
; SSE4-NEXT: retq
;
; AVX1-LABEL: test_intrinsic_fminf:
; AVX1: # %bb.0:
Expand All @@ -142,17 +169,26 @@ define float @test_intrinsic_fminf(float %x, float %y) {
}

define double @test_intrinsic_fmin(double %x, double %y) {
; SSE-LABEL: test_intrinsic_fmin:
; SSE: # %bb.0:
; SSE-NEXT: movapd %xmm0, %xmm2
; SSE-NEXT: cmpunordsd %xmm0, %xmm2
; SSE-NEXT: movapd %xmm2, %xmm3
; SSE-NEXT: andpd %xmm1, %xmm3
; SSE-NEXT: minsd %xmm0, %xmm1
; SSE-NEXT: andnpd %xmm1, %xmm2
; SSE-NEXT: orpd %xmm3, %xmm2
; SSE-NEXT: movapd %xmm2, %xmm0
; SSE-NEXT: retq
; SSE2-LABEL: test_intrinsic_fmin:
; SSE2: # %bb.0:
; SSE2-NEXT: movapd %xmm0, %xmm2
; SSE2-NEXT: cmpunordsd %xmm0, %xmm2
; SSE2-NEXT: movapd %xmm2, %xmm3
; SSE2-NEXT: andpd %xmm1, %xmm3
; SSE2-NEXT: minsd %xmm0, %xmm1
; SSE2-NEXT: andnpd %xmm1, %xmm2
; SSE2-NEXT: orpd %xmm3, %xmm2
; SSE2-NEXT: movapd %xmm2, %xmm0
; SSE2-NEXT: retq
;
; SSE4-LABEL: test_intrinsic_fmin:
; SSE4: # %bb.0:
; SSE4-NEXT: movapd %xmm1, %xmm2
; SSE4-NEXT: minsd %xmm0, %xmm2
; SSE4-NEXT: cmpunordsd %xmm0, %xmm0
; SSE4-NEXT: blendvpd %xmm0, %xmm1, %xmm2
; SSE4-NEXT: movapd %xmm2, %xmm0
; SSE4-NEXT: retq
;
; AVX1-LABEL: test_intrinsic_fmin:
; AVX1: # %bb.0:
Expand Down
10 changes: 4 additions & 6 deletions llvm/test/CodeGen/X86/fp-select-cmp-and.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -189,10 +189,9 @@ define float @test17(float %a, float %b, float %c, float %eps) {
; CHECK-LABEL: test17:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpless %xmm0, %xmm3
; CHECK-NEXT: andps %xmm3, %xmm2
; CHECK-NEXT: andnps %xmm1, %xmm3
; CHECK-NEXT: orps %xmm2, %xmm3
; CHECK-NEXT: movaps %xmm3, %xmm0
; CHECK-NEXT: blendvps %xmm0, %xmm2, %xmm1
; CHECK-NEXT: movaps %xmm1, %xmm0
; CHECK-NEXT: retq
%cmp = fcmp oge float %a, %eps
%cond = select i1 %cmp, float %c, float %b
Expand All @@ -203,10 +202,9 @@ define double @test18(double %a, double %b, double %c, double %eps) {
; CHECK-LABEL: test18:
; CHECK: # %bb.0:
; CHECK-NEXT: cmplesd %xmm0, %xmm3
; CHECK-NEXT: andpd %xmm3, %xmm2
; CHECK-NEXT: andnpd %xmm1, %xmm3
; CHECK-NEXT: orpd %xmm2, %xmm3
; CHECK-NEXT: movapd %xmm3, %xmm0
; CHECK-NEXT: blendvpd %xmm0, %xmm2, %xmm1
; CHECK-NEXT: movapd %xmm1, %xmm0
; CHECK-NEXT: retq
%cmp = fcmp oge double %a, %eps
%cond = select i1 %cmp, double %c, double %b
Expand Down
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