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31 changes: 31 additions & 0 deletions llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -8652,6 +8652,37 @@ bool ARMAsmParser::validateInstruction(MCInst &Inst,
"coprocessor must be configured as GCP");
break;
}

case ARM::VTOSHH:
case ARM::VTOUHH:
case ARM::VTOSLH:
case ARM::VTOULH:
case ARM::VTOSHS:
case ARM::VTOUHS:
case ARM::VTOSLS:
case ARM::VTOULS:
case ARM::VTOSHD:
case ARM::VTOUHD:
case ARM::VTOSLD:
case ARM::VTOULD:
case ARM::VSHTOH:
case ARM::VUHTOH:
case ARM::VSLTOH:
case ARM::VULTOH:
case ARM::VSHTOS:
case ARM::VUHTOS:
case ARM::VSLTOS:
case ARM::VULTOS:
case ARM::VSHTOD:
case ARM::VUHTOD:
case ARM::VSLTOD:
case ARM::VULTOD: {
if (Operands[MnemonicOpsEndInd]->getReg() !=
Operands[MnemonicOpsEndInd + 1]->getReg())
return Error(Operands[MnemonicOpsEndInd]->getStartLoc(),
"source and destination registers must be the same");
break;
}
}

return false;
Expand Down
51 changes: 51 additions & 0 deletions llvm/test/MC/ARM/vcvt-fixed-point-errors.s
Original file line number Diff line number Diff line change
@@ -0,0 +1,51 @@
// RUN: not llvm-mc -triple=armv8a-none-eabi -mattr=+fullfp16 < %s 2>&1 | FileCheck %s

vcvt.u16.f16 s0, s1, #1
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
vcvt.s16.f16 s0, s1, #1
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
vcvt.u32.f16 s0, s1, #1
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
vcvt.s32.f16 s0, s1, #1
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
vcvt.u16.f32 s0, s1, #1
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
vcvt.s16.f32 s0, s1, #1
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
vcvt.u32.f32 s0, s1, #1
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
vcvt.s32.f32 s0, s1, #1
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
vcvt.u16.f64 d0, d1, #1
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
vcvt.s16.f64 d0, d1, #1
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
vcvt.u32.f64 d0, d1, #1
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
vcvt.s32.f64 d0, d1, #1
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
vcvt.f16.u16 s0, s1, #1
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
vcvt.f16.s16 s0, s1, #1
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
vcvt.f16.u32 s0, s1, #1
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
vcvt.f16.s32 s0, s1, #1
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
vcvt.f32.u16 s0, s1, #1
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
vcvt.f32.s16 s0, s1, #1
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
vcvt.f32.u32 s0, s1, #1
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
vcvt.f32.s32 s0, s1, #1
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
vcvt.f64.u16 d0, d1, #1
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
vcvt.f64.s16 d0, d1, #1
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
vcvt.f64.u32 d0, d1, #1
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same
vcvt.f64.s32 d0, d1, #1
// CHECK: [[@LINE-1]]{{.*}}error: source and destination registers must be the same