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[X86] Combine FRINT + FP_TO_SINT to LRINT #126477

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Merged
merged 5 commits into from
Feb 21, 2025
Merged

[X86] Combine FRINT + FP_TO_SINT to LRINT #126477

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2225596
[X86] Combine FRINT + FP_TO_SINT to LRINT
phoebewang Feb 10, 2025
9a70a3e
Remove fast math constraint
phoebewang Feb 10, 2025
f7eb84b
Add v2f64 / v4f64 cases and AVX test coverage
phoebewang Feb 10, 2025
d6a1fa3
Merge branch 'main' into rint
phoebewang Feb 11, 2025
114d435
Check SSE2
phoebewang Feb 17, 2025
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13 changes: 13 additions & 0 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2684,6 +2684,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
ISD::ZERO_EXTEND_VECTOR_INREG,
ISD::SINT_TO_FP,
ISD::UINT_TO_FP,
ISD::FP_TO_SINT,
ISD::STRICT_SINT_TO_FP,
ISD::STRICT_UINT_TO_FP,
ISD::FP_TO_SINT_SAT,
Expand Down Expand Up @@ -56380,6 +56381,17 @@ static SDValue combineSIntToFP(SDNode *N, SelectionDAG &DAG,
return SDValue();
}

static SDValue combineFPToSInt(SDNode *N, SelectionDAG &DAG,
const X86Subtarget &Subtarget) {
EVT VT = N->getValueType(0);
SDValue Src = N->getOperand(0);
if (Src.getOpcode() == ISD::FRINT && VT.getScalarType() == MVT::i32 &&
Src.hasOneUse())
return DAG.getNode(ISD::LRINT, SDLoc(N), VT, Src.getOperand(0));
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@RKSimon RKSimon Feb 10, 2025

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I'm assuming this is OK if it fires for vcvtph2dq?

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@topperc topperc Feb 10, 2025

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Do we need to check soft float and no-sse+no-x87 to avoid creating libcalls with the wrong register? Maybe isTypeLegal for the FP type is enough?

Do we need to check f16 is legal?

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@phoebewang phoebewang Feb 16, 2025

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I'm assuming this is OK if it fires for vcvtph2dq?

Good question! We need to support LRINT for FP16 first: #127382

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@phoebewang phoebewang Feb 16, 2025

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Do we need to check soft float and no-sse+no-x87 to avoid creating libcalls with the wrong register? Maybe isTypeLegal for the FP type is enough?

I don't think so. It is different with #126217, 1) we don't combine TRUNC this time, so we won't eliminate ZEXT; 2) we based on the fact the out of range result is UB. We don't care the result in this case.

Do we need to check f16 is legal?

I think it doesn't matter. 1) if the f16 is not legal, the ABI is broken, it's UB to the compiler; 2) we don't have f16 math library so far, the lowering for f16 FRINT/LRINT is not supported for now.

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@topperc topperc Feb 16, 2025

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Do we need to check soft float and no-sse+no-x87 to avoid creating libcalls with the wrong register? Maybe isTypeLegal for the FP type is enough?

I don't think so. It is different with #126217, 1) we don't combine TRUNC this time, so we won't eliminate ZEXT; 2) we based on the fact the out of range result is UB. We don't care the result in this case.

I think creating libcalls with the wrong register class is in general a bad idea even we can't find a functional issue with it.

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@phoebewang phoebewang Feb 17, 2025

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Do we need to check soft float and no-sse+no-x87 to avoid creating libcalls with the wrong register? Maybe isTypeLegal for the FP type is enough?

I don't think so. It is different with #126217, 1) we don't combine TRUNC this time, so we won't eliminate ZEXT; 2) we based on the fact the out of range result is UB. We don't care the result in this case.

I think creating libcalls with the wrong register class is in general a bad idea even we can't find a functional issue with it.

Add checking for SSE2.


return SDValue();
}

// Custom handling for VCVTTPS2QQS/VCVTTPS2UQQS
static SDValue combineFP_TO_xINT_SAT(SDNode *N, SelectionDAG &DAG,
const X86Subtarget &Subtarget) {
Expand Down Expand Up @@ -59405,6 +59417,7 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
case ISD::UINT_TO_FP:
case ISD::STRICT_UINT_TO_FP:
return combineUIntToFP(N, DAG, Subtarget);
case ISD::FP_TO_SINT: return combineFPToSInt(N, DAG, Subtarget);
case ISD::LRINT:
case ISD::LLRINT: return combineLRINT_LLRINT(N, DAG, Subtarget);
case ISD::FADD:
Expand Down
51 changes: 51 additions & 0 deletions llvm/test/CodeGen/X86/rint-conv.ll
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@@ -0,0 +1,51 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=X86
; RUN: llc < %s -mtriple=x86_64-unknown | FileCheck %s --check-prefixes=X64

define i32 @combine_f32(float %x) nounwind {
; X86-LABEL: combine_f32:
; X86: # %bb.0: # %entry
; X86-NEXT: cvtss2si {{[0-9]+}}(%esp), %eax
; X86-NEXT: retl
;
; X64-LABEL: combine_f32:
; X64: # %bb.0: # %entry
; X64-NEXT: cvtss2si %xmm0, %eax
; X64-NEXT: retq
entry:
%0 = tail call float @llvm.rint.f32(float %x)
%1 = fptosi float %0 to i32
ret i32 %1
}

define i32 @combine_f64(double %x) nounwind {
; X86-LABEL: combine_f64:
; X86: # %bb.0: # %entry
; X86-NEXT: cvtsd2si {{[0-9]+}}(%esp), %eax
; X86-NEXT: retl
;
; X64-LABEL: combine_f64:
; X64: # %bb.0: # %entry
; X64-NEXT: cvtsd2si %xmm0, %eax
; X64-NEXT: retq
entry:
%0 = tail call double @llvm.rint.f32(double %x)
%1 = fptosi double %0 to i32
ret i32 %1
}

define <4 x i32> @combine_v4f32(<4 x float> %x) nounwind {
; X86-LABEL: combine_v4f32:
; X86: # %bb.0: # %entry
; X86-NEXT: cvtps2dq %xmm0, %xmm0
; X86-NEXT: retl
;
; X64-LABEL: combine_v4f32:
; X64: # %bb.0: # %entry
; X64-NEXT: cvtps2dq %xmm0, %xmm0
; X64-NEXT: retq
entry:
%0 = tail call <4 x float> @llvm.rint.v4f32(<4 x float> %x)
%1 = fptosi <4 x float> %0 to <4 x i32>
ret <4 x i32> %1
}