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Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" #126684

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Merged
merged 3 commits into from
Feb 12, 2025
Merged

Reland "CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)" #126684

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cf6a51d
CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)
cdevadas Feb 5, 2025
b047c56
Regression fix: store impl class as member
optimisan Feb 11, 2025
dabe875
Add fixmes noting the scheduled removal of forward decls
optimisan Feb 12, 2025
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28 changes: 28 additions & 0 deletions llvm/include/llvm/CodeGen/MachineScheduler.h
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Original file line number Diff line number Diff line change
Expand Up @@ -98,6 +98,10 @@
#include <vector>

namespace llvm {
namespace impl_detail {
class MachineSchedulerImpl;
class PostMachineSchedulerImpl;
} // namespace impl_detail
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I don't think these should need to be exposed in the header

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I want these Impl classes to be members in the new pass in this header. (workaround for RegisterClassInfo not being an analysis yet)

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So we can drop this after the analysis change is made?

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Yes


namespace MISched {
enum Direction {
Expand Down Expand Up @@ -1385,6 +1389,30 @@ std::unique_ptr<ScheduleDAGMutation>
createCopyConstrainDAGMutation(const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI);

class MachineSchedulerPass : public PassInfoMixin<MachineSchedulerPass> {
std::unique_ptr<impl_detail::MachineSchedulerImpl> Impl;
const TargetMachine *TM;

public:
MachineSchedulerPass(const TargetMachine *TM);
MachineSchedulerPass(MachineSchedulerPass &&Other);
~MachineSchedulerPass();
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
};

class PostMachineSchedulerPass
: public PassInfoMixin<PostMachineSchedulerPass> {
std::unique_ptr<impl_detail::PostMachineSchedulerImpl> Impl;
const TargetMachine *TM;

public:
PostMachineSchedulerPass(const TargetMachine *TM);
PostMachineSchedulerPass(PostMachineSchedulerPass &&Other);
~PostMachineSchedulerPass();
PreservedAnalyses run(MachineFunction &MF,
MachineFunctionAnalysisManager &MFAM);
};
} // end namespace llvm

#endif // LLVM_CODEGEN_MACHINESCHEDULER_H
4 changes: 2 additions & 2 deletions llvm/include/llvm/InitializePasses.h
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Expand Up @@ -209,7 +209,7 @@ void initializeMachinePipelinerPass(PassRegistry &);
void initializeMachinePostDominatorTreeWrapperPassPass(PassRegistry &);
void initializeMachineRegionInfoPassPass(PassRegistry &);
void initializeMachineSanitizerBinaryMetadataPass(PassRegistry &);
void initializeMachineSchedulerPass(PassRegistry &);
void initializeMachineSchedulerLegacyPass(PassRegistry &);
void initializeMachineSinkingPass(PassRegistry &);
void initializeMachineTraceMetricsWrapperPassPass(PassRegistry &);
void initializeMachineUniformityInfoPrinterPassPass(PassRegistry &);
Expand Down Expand Up @@ -238,7 +238,7 @@ void initializePostDomPrinterWrapperPassPass(PassRegistry &);
void initializePostDomViewerWrapperPassPass(PassRegistry &);
void initializePostDominatorTreeWrapperPassPass(PassRegistry &);
void initializePostInlineEntryExitInstrumenterPass(PassRegistry &);
void initializePostMachineSchedulerPass(PassRegistry &);
void initializePostMachineSchedulerLegacyPass(PassRegistry &);
void initializePostRAHazardRecognizerPass(PassRegistry &);
void initializePostRAMachineSinkingPass(PassRegistry &);
void initializePostRASchedulerLegacyPass(PassRegistry &);
Expand Down
5 changes: 3 additions & 2 deletions llvm/include/llvm/Passes/CodeGenPassBuilder.h
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Expand Up @@ -50,6 +50,7 @@
#include "llvm/CodeGen/MachineLICM.h"
#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/MachineVerifier.h"
#include "llvm/CodeGen/OptimizePHIs.h"
#include "llvm/CodeGen/PHIElimination.h"
Expand Down Expand Up @@ -960,7 +961,7 @@ Error CodeGenPassBuilder<Derived, TargetMachineT>::addMachinePasses(
if (getOptLevel() != CodeGenOptLevel::None &&
!TM.targetSchedulesPostRAScheduling()) {
if (Opt.MISchedPostRA)
addPass(PostMachineSchedulerPass());
addPass(PostMachineSchedulerPass(&TM));
else
addPass(PostRASchedulerPass(&TM));
}
Expand Down Expand Up @@ -1144,7 +1145,7 @@ void CodeGenPassBuilder<Derived, TargetMachineT>::addOptimizedRegAlloc(
addPass(RenameIndependentSubregsPass());

// PreRA instruction scheduling.
addPass(MachineSchedulerPass());
addPass(MachineSchedulerPass(&TM));

if (derived().addRegAssignmentOptimized(addPass)) {
// Allow targets to expand pseudo instructions depending on the choice of
Expand Down
4 changes: 2 additions & 2 deletions llvm/include/llvm/Passes/MachinePassRegistry.def
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Expand Up @@ -142,12 +142,14 @@ MACHINE_FUNCTION_PASS("finalize-isel", FinalizeISelPass())
MACHINE_FUNCTION_PASS("localstackalloc", LocalStackSlotAllocationPass())
MACHINE_FUNCTION_PASS("machine-cp", MachineCopyPropagationPass())
MACHINE_FUNCTION_PASS("machine-cse", MachineCSEPass())
MACHINE_FUNCTION_PASS("machine-scheduler", MachineSchedulerPass(TM))
MACHINE_FUNCTION_PASS("machinelicm", MachineLICMPass())
MACHINE_FUNCTION_PASS("no-op-machine-function", NoOpMachineFunctionPass())
MACHINE_FUNCTION_PASS("opt-phis", OptimizePHIsPass())
MACHINE_FUNCTION_PASS("peephole-opt", PeepholeOptimizerPass())
MACHINE_FUNCTION_PASS("phi-node-elimination", PHIEliminationPass())
MACHINE_FUNCTION_PASS("post-RA-sched", PostRASchedulerPass(TM))
MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass(TM))
MACHINE_FUNCTION_PASS("print", PrintMIRPass())
MACHINE_FUNCTION_PASS("print<livedebugvars>", LiveDebugVariablesPrinterPass(errs()))
MACHINE_FUNCTION_PASS("print<live-intervals>", LiveIntervalsPrinterPass(errs()))
Expand Down Expand Up @@ -243,13 +245,11 @@ DUMMY_MACHINE_FUNCTION_PASS("static-data-splitter", StaticDataSplitter)
DUMMY_MACHINE_FUNCTION_PASS("machine-function-splitter", MachineFunctionSplitterPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-latecleanup", MachineLateInstrsCleanupPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-sanmd", MachineSanitizerBinaryMetadata)
DUMMY_MACHINE_FUNCTION_PASS("machine-scheduler", MachineSchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-sink", MachineSinkingPass)
DUMMY_MACHINE_FUNCTION_PASS("machine-uniformity", MachineUniformityInfoWrapperPass)
DUMMY_MACHINE_FUNCTION_PASS("machineinstr-printer", MachineFunctionPrinterPass)
DUMMY_MACHINE_FUNCTION_PASS("mirfs-discriminators", MIRAddFSDiscriminatorsPass)
DUMMY_MACHINE_FUNCTION_PASS("patchable-function", PatchableFunctionPass)
DUMMY_MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass)
DUMMY_MACHINE_FUNCTION_PASS("postra-machine-sink", PostRAMachineSinkingPass)
DUMMY_MACHINE_FUNCTION_PASS("postrapseudos", ExpandPostRAPseudosPass)
DUMMY_MACHINE_FUNCTION_PASS("print-machine-cycles", MachineCycleInfoPrinterPass)
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/CodeGen.cpp
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Expand Up @@ -94,7 +94,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeModuloScheduleTestPass(Registry);
initializeMachinePostDominatorTreeWrapperPassPass(Registry);
initializeMachineRegionInfoPassPass(Registry);
initializeMachineSchedulerPass(Registry);
initializeMachineSchedulerLegacyPass(Registry);
initializeMachineSinkingPass(Registry);
initializeMachineUniformityAnalysisPassPass(Registry);
initializeMachineUniformityInfoPrinterPassPass(Registry);
Expand All @@ -105,7 +105,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializePHIEliminationPass(Registry);
initializePatchableFunctionPass(Registry);
initializePeepholeOptimizerLegacyPass(Registry);
initializePostMachineSchedulerPass(Registry);
initializePostMachineSchedulerLegacyPass(Registry);
initializePostRAHazardRecognizerPass(Registry);
initializePostRAMachineSinkingPass(Registry);
initializePostRASchedulerLegacyPass(Registry);
Expand Down
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