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[X86] combineConcatVectorOps - fold concat(EXTEND_VECTOR_INREG(x),EXTEND_VECTOR_INREG(y)) -> EXTEND_VECTOR_INREG(unpack(x,y)) #127502

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Merged
merged 1 commit into from
Feb 17, 2025
Merged

[X86] combineConcatVectorOps - fold concat(EXTEND_VECTOR_INREG(x),EXTEND_VECTOR_INREG(y)) -> EXTEND_VECTOR_INREG(unpack(x,y)) #127502

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45 changes: 42 additions & 3 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4679,9 +4679,24 @@ static SDValue getEXTEND_VECTOR_INREG(unsigned Opcode, const SDLoc &DL, EVT VT,
SDValue In, SelectionDAG &DAG) {
EVT InVT = In.getValueType();
assert(VT.isVector() && InVT.isVector() && "Expected vector VTs.");
assert((ISD::ANY_EXTEND == Opcode || ISD::SIGN_EXTEND == Opcode ||
ISD::ZERO_EXTEND == Opcode) &&
"Unknown extension opcode");

// Canonicalize Opcode to general extension version.
switch (Opcode) {
case ISD::ANY_EXTEND:
case ISD::ANY_EXTEND_VECTOR_INREG:
Opcode = ISD::ANY_EXTEND;
break;
case ISD::SIGN_EXTEND:
case ISD::SIGN_EXTEND_VECTOR_INREG:
Opcode = ISD::SIGN_EXTEND;
break;
case ISD::ZERO_EXTEND:
case ISD::ZERO_EXTEND_VECTOR_INREG:
Opcode = ISD::ZERO_EXTEND;
break;
default:
llvm_unreachable("Unknown extension opcode");
}

// For 256-bit vectors, we only need the lower (128-bit) input half.
// For 512-bit vectors, we only need the lower input half or quarter.
Expand Down Expand Up @@ -57864,6 +57879,30 @@ static SDValue combineConcatVectorOps(const SDLoc &DL, MVT VT,
}
}
break;
case ISD::ANY_EXTEND_VECTOR_INREG:
case ISD::SIGN_EXTEND_VECTOR_INREG:
case ISD::ZERO_EXTEND_VECTOR_INREG: {
// TODO: Handle ANY_EXTEND combos with SIGN/ZERO_EXTEND.
if (!IsSplat && NumOps == 2 && VT.is256BitVector() &&
Subtarget.hasInt256() &&
Op0.getOperand(0).getValueType().is128BitVector() &&
Op0.getOperand(0).getValueType() ==
Ops[0].getOperand(0).getValueType()) {
EVT SrcVT = Op0.getOperand(0).getValueType();
unsigned NumElts = VT.getVectorNumElements();
MVT UnpackSVT =
MVT::getIntegerVT(SrcVT.getScalarSizeInBits() * (NumElts / 2));
MVT UnpackVT =
MVT::getVectorVT(UnpackSVT, 128 / UnpackSVT.getScalarSizeInBits());
SDValue Unpack =
DAG.getNode(X86ISD::UNPCKL, DL, UnpackVT,
DAG.getBitcast(UnpackVT, Ops[0].getOperand(0)),
DAG.getBitcast(UnpackVT, Ops[1].getOperand(0)));
return getEXTEND_VECTOR_INREG(Op0.getOpcode(), DL, VT,
DAG.getBitcast(SrcVT, Unpack), DAG);
}
break;
}
case X86ISD::VSHLI:
case X86ISD::VSRLI:
// Special case: SHL/SRL AVX1 V4i64 by 32-bits can lower as a shuffle.
Expand Down
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