Adding support in llvm-exegesis for Aarch64 for handling FPR64/128, PPR16 and ZPR128 reg class.

llvm/test/tools/llvm-exegesis/AArch64/reg_based/reg_fpr128.s

@@ -0,0 +1,8 @@
+# RUN: llvm-exegesis -mcpu=neoverse-v2 -mode=latency -opcode-name=ADDVv16i8v | FileCheck %s
+# REQUIRES: aarch64-registered-target
+
+# Check that warning of not initializing registers is not printed
+# CHECK-NOT: setRegTo is not implemented, results will be unreliable
+
+# Check that we add ret (bx lr) instr to snippet
+# CHECK: assembled_snippet: {{.*}}C0035FD6

llvm/test/tools/llvm-exegesis/AArch64/reg_based/reg_fpr64.s

@@ -0,0 +1,7 @@
+# RUN: llvm-exegesis -mcpu=neoverse-v2 -mode=latency -opcode-name=ADDVv4i16v 2>&1 | FileCheck %s
+
+# Check that warning of not initializing registers is not printed
+# CHECK-NOT: setRegTo is not implemented, results will be unreliable
+
+# Check that we add ret (bx lr) instr to snippet
+# CHECK: assembled_snippet: {{.*}}C0035FD6

llvm/test/tools/llvm-exegesis/AArch64/reg_based/reg_ppr.s

@@ -0,0 +1,8 @@
+# RUN: llvm-exegesis -mcpu=neoverse-v2 -mode=latency -opcode-name=FADDV_VPZ_D | FileCheck %s
+# REQUIRES: aarch64-registered-target
+
+# Check that warning of not initializing registers is not printed
+# CHECK-NOT: setRegTo is not implemented, results will be unreliable
+
+# Check that we add ret (bx lr) instr to snippet
+# CHECK: assembled_snippet: {{.*}}C0035FD6

llvm/test/tools/llvm-exegesis/AArch64/reg_based/reg_zpr.s

@@ -0,0 +1,8 @@
+# RUN: llvm-exegesis -mcpu=neoverse-v2 -mode=latency -opcode-name=FADDV_VPZ_S | FileCheck %s
+# REQUIRES: aarch64-registered-target
+
+# Check that warning of not initializing registers is not printed
+# CHECK-NOT: setRegTo is not implemented, results will be unreliable
+
+# Check that we add ret (bx lr) instr to snippet
+# CHECK: assembled_snippet: {{.*}}C0035FD6

llvm/tools/llvm-exegesis/lib/AArch64/Target.cpp

@@ -28,31 +28,28 @@ static unsigned getLoadImmediateOpcode(unsigned RegBitWidth) {
 // Generates instruction to load an immediate value into a register.
 static MCInst loadImmediate(MCRegister Reg, unsigned RegBitWidth,
                             const APInt &Value) {
-  if (Value.getBitWidth() > RegBitWidth)
-    llvm_unreachable("Value must fit in the Register");
+  assert(Value.getBitWidth() <= RegBitWidth && "Value must fit in the Register"); 
   return MCInstBuilder(getLoadImmediateOpcode(RegBitWidth))
       .addReg(Reg)
       .addImm(Value.getZExtValue());
 }
 
 static MCInst loadZPRImmediate(MCRegister Reg, unsigned RegBitWidth,
                                const APInt &Value) {
-  if (Value.getBitWidth() > RegBitWidth)
-    llvm_unreachable("Value must fit in the ZPR Register");
+  assert(Value.getBitWidth() <= RegBitWidth && "Value must fit in the PPR Register");
   // For ZPR, we typically use DUPM instruction to load immediate values
   return MCInstBuilder(AArch64::DUPM_ZI)
       .addReg(Reg)
-      .addImm(Value.getZExtValue());
+      .addImm(0x1);
 }
 
 static MCInst loadPPRImmediate(MCRegister Reg, unsigned RegBitWidth,
                                const APInt &Value) {
-  if (Value.getBitWidth() > RegBitWidth)
-    llvm_unreachable("Value must fit in the PPR Register");
+  assert(Value.getBitWidth() <= RegBitWidth && "Value must fit in the PPR Register"); 
   // For PPR, we typically use PTRUE instruction to set predicate registers
   return MCInstBuilder(AArch64::PTRUE_B)
       .addReg(Reg)
-      .addImm(31); // All lanes true
+      .addImm(0xFFFF); // All lanes true for 16 bits
 }
 
 // Generates instruction to load an FP immediate value into a register.
@@ -70,8 +67,7 @@ static unsigned getLoadFPImmediateOpcode(unsigned RegBitWidth) {
 // Generates instruction to load an FP immediate value into a register.
 static MCInst loadFPImmediate(MCRegister Reg, unsigned RegBitWidth,
                             const APInt &Value) {
-  if (Value.getBitWidth() > RegBitWidth)
-    llvm_unreachable("Value must fit in the FP Register");
+  assert(Value.getBitWidth() <= RegBitWidth && "Value must fit in the FP Register");
   return MCInstBuilder(getLoadFPImmediateOpcode(RegBitWidth))
       .addReg(Reg)
       .addImm(Value.getZExtValue());
@@ -131,4 +127,4 @@ void InitializeAArch64ExegesisTarget() {
 }
 
 } // namespace exegesis
-} // namespace llvm
+} // namespace llvm