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[GlobalISel][AArch64] Fix fptoi.sat lowering. #127901

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Merged
davemgreen merged 2 commits into from
Feb 20, 2025
Merged

[GlobalISel][AArch64] Fix fptoi.sat lowering. #127901

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[GlobalISel][AArch64] Fix fptoi.sat lowering.
davemgreen Feb 19, 2025
cdeb2b0
Switch to ogt
davemgreen Feb 20, 2025
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4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -7816,13 +7816,13 @@ LegalizerHelper::lowerFPTOINT_SAT(MachineInstr &MI) {
if (AreExactFloatBounds) {
// Clamp Src by MinFloat from below. If Src is NaN the result is MinFloat.
auto MaxC = MIRBuilder.buildFConstant(SrcTy, MinFloat);
auto MaxP = MIRBuilder.buildFCmp(CmpInst::FCMP_ULT,
auto MaxP = MIRBuilder.buildFCmp(CmpInst::FCMP_UGT,
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@nikic nikic Feb 19, 2025

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Should this be OGT? Otherwise we'll select Src if Src is NaN, while we want to select zero.

SrcTy.changeElementSize(1), Src, MaxC);
auto Max = MIRBuilder.buildSelect(SrcTy, MaxP, Src, MaxC);
// Clamp by MaxFloat from above. NaN cannot occur.
auto MinC = MIRBuilder.buildFConstant(SrcTy, MaxFloat);
auto MinP =
MIRBuilder.buildFCmp(CmpInst::FCMP_OGT, SrcTy.changeElementSize(1), Max,
MIRBuilder.buildFCmp(CmpInst::FCMP_OLT, SrcTy.changeElementSize(1), Max,
MinC, MachineInstr::FmNoNans);
auto Min =
MIRBuilder.buildSelect(SrcTy, MinP, Max, MinC, MachineInstr::FmNoNans);
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12 changes: 6 additions & 6 deletions llvm/test/CodeGen/AArch64/fptosi-sat-scalar.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -987,25 +987,25 @@ define i32 @test_signed_f128_i32(fp128 %f) {
; CHECK-GI-NEXT: adrp x8, .LCPI30_1
; CHECK-GI-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_1]
; CHECK-GI-NEXT: bl __getf2
; CHECK-GI-NEXT: bl __letf2
; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: mov x9, #-4603241769126068224 // =0xc01e000000000000
; CHECK-GI-NEXT: fmov x8, d0
; CHECK-GI-NEXT: csel x19, x8, xzr, lt
; CHECK-GI-NEXT: csel x19, x8, xzr, gt
; CHECK-GI-NEXT: mov x8, v0.d[1]
; CHECK-GI-NEXT: mov v0.d[0], x19
; CHECK-GI-NEXT: csel x20, x8, x9, lt
; CHECK-GI-NEXT: csel x20, x8, x9, gt
; CHECK-GI-NEXT: adrp x8, .LCPI30_0
; CHECK-GI-NEXT: mov v0.d[1], x20
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI30_0]
; CHECK-GI-NEXT: bl __gttf2
; CHECK-GI-NEXT: bl __lttf2
; CHECK-GI-NEXT: cmp w0, #0
; CHECK-GI-NEXT: csel x8, x19, xzr, gt
; CHECK-GI-NEXT: csel x8, x19, xzr, lt
; CHECK-GI-NEXT: mov v0.d[0], x8
; CHECK-GI-NEXT: mov x8, #281474976448512 // =0xfffffffc0000
; CHECK-GI-NEXT: movk x8, #16413, lsl #48
; CHECK-GI-NEXT: csel x8, x20, x8, gt
; CHECK-GI-NEXT: csel x8, x20, x8, lt
; CHECK-GI-NEXT: mov v0.d[1], x8
; CHECK-GI-NEXT: bl __fixtfsi
; CHECK-GI-NEXT: ldr q0, [sp] // 16-byte Folded Reload
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