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[mlir] [Vector] Add IndexBitWidth option to vector-to-llvm pass #128154

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[mlir] [Vector] Add IndexBitWidth option to vector-to-llvm pass #128154

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3 changes: 3 additions & 0 deletions mlir/include/mlir/Conversion/Passes.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1414,6 +1414,9 @@ def ConvertVectorToLLVMPass : Pass<"convert-vector-to-llvm"> {
"vector::VectorTransformsOptions",
/*default=*/"vector::VectorTransformsOptions()",
"Options to lower some operations like contractions and transposes.">,
Option<"indexBitwidth", "index-bitwidth", "unsigned",
/*default=kDeriveIndexBitwidthFromDataLayout*/"0",
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@dcaballe dcaballe Feb 21, 2025

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Cool! How this derive index bitwidth from data layout works? Is there a single bitwidth per module? It would be great if we could extend this to have a bitwidth per address space at some point :)

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@quic-rb10 quic-rb10 Feb 27, 2025 •
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@dcaballe Could you please elaborate on this? I have added some of my findings regarding the indexbitwidth from datalayout as a reply to another one of your comments.

"Bitwidth of the index type, 0 to use size of machine word">,
];
}

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23 changes: 13 additions & 10 deletions mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp
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Expand Up @@ -1439,8 +1439,6 @@ class VectorTypeCastOpConversion
if (llvm::any_of(*targetStrides, ShapedType::isDynamic))
return failure();

auto int64Ty = IntegerType::get(rewriter.getContext(), 64);

// Create descriptor.
auto desc = MemRefDescriptor::poison(rewriter, loc, llvmTargetDescriptorTy);
// Set allocated ptr.
Expand All @@ -1451,21 +1449,26 @@ class VectorTypeCastOpConversion
Value ptr = sourceMemRef.alignedPtr(rewriter, loc);
desc.setAlignedPtr(rewriter, loc, ptr);
// Fill offset 0.
auto attr = rewriter.getIntegerAttr(rewriter.getIndexType(), 0);
auto zero = rewriter.create<LLVM::ConstantOp>(loc, int64Ty, attr);

auto idxType = rewriter.getIndexType();
auto zero = rewriter.create<LLVM::ConstantOp>(
loc, typeConverter->convertType(idxType),
rewriter.getIntegerAttr(idxType, 0));
desc.setOffset(rewriter, loc, zero);

// Fill size and stride descriptors in memref.
for (const auto &indexedSize :
llvm::enumerate(targetMemRefType.getShape())) {
int64_t index = indexedSize.index();
auto sizeAttr =
rewriter.getIntegerAttr(rewriter.getIndexType(), indexedSize.value());
auto size = rewriter.create<LLVM::ConstantOp>(loc, int64Ty, sizeAttr);

auto size = rewriter.create<LLVM::ConstantOp>(
loc, typeConverter->convertType(idxType),
rewriter.getIntegerAttr(idxType, indexedSize.value()));
desc.setSize(rewriter, loc, index, size);
auto strideAttr = rewriter.getIntegerAttr(rewriter.getIndexType(),
(*targetStrides)[index]);
auto stride = rewriter.create<LLVM::ConstantOp>(loc, int64Ty, strideAttr);

auto stride = rewriter.create<LLVM::ConstantOp>(
loc, typeConverter->convertType(idxType),
rewriter.getIntegerAttr(idxType, (*targetStrides)[index]));
desc.setStride(rewriter, loc, index, stride);
}

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12 changes: 8 additions & 4 deletions mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVMPass.cpp
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Expand Up @@ -7,7 +7,7 @@
//===----------------------------------------------------------------------===//

#include "mlir/Conversion/VectorToLLVM/ConvertVectorToLLVMPass.h"

#include "mlir/Analysis/DataLayoutAnalysis.h"
#include "mlir/Conversion/LLVMCommon/ConversionTarget.h"
#include "mlir/Conversion/LLVMCommon/TypeConverter.h"
#include "mlir/Dialect/AMX/AMXDialect.h"
Expand Down Expand Up @@ -64,6 +64,8 @@ void ConvertVectorToLLVMPass::runOnOperation() {
// Perform progressive lowering of operations on slices and all contraction
// operations. Also materializes masks, lowers vector.step, rank-reduces FMA,
// applies folding and DCE.
Operation *op = getOperation();
const auto &dataLayoutAnalysis = getAnalysis<DataLayoutAnalysis>();
{
RewritePatternSet patterns(&getContext());
populateVectorToVectorCanonicalizationPatterns(patterns);
Expand All @@ -83,10 +85,12 @@ void ConvertVectorToLLVMPass::runOnOperation() {
populateVectorRankReducingFMAPattern(patterns);
(void)applyPatternsGreedily(getOperation(), std::move(patterns));
}

// Convert to the LLVM IR dialect.
LowerToLLVMOptions options(&getContext());
LLVMTypeConverter converter(&getContext(), options);
LowerToLLVMOptions options(&getContext(),
dataLayoutAnalysis.getAtOrAbove(op));
if (indexBitwidth != kDeriveIndexBitwidthFromDataLayout)
options.overrideIndexBitwidth(indexBitwidth);
LLVMTypeConverter converter(&getContext(), options, &dataLayoutAnalysis);
RewritePatternSet patterns(&getContext());
populateVectorTransferLoweringPatterns(patterns);
populateVectorToLLVMMatrixConversionPatterns(converter, patterns);
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25 changes: 25 additions & 0 deletions mlir/test/Conversion/VectorToLLVM/vector-datalayout-bitwidth.mlir
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@@ -0,0 +1,25 @@
// RUN: mlir-opt %s -convert-vector-to-llvm -split-input-file | FileCheck %s

module attributes {dlti.dl_spec = #dlti.dl_spec< #dlti.dl_entry<index, 32>>} {
// CHECK-LABEL: func.func @broadcast_vec2d_from_vec0d(
// CHECK-SAME: %[[VAL_0:[0-9]+|[a-zA-Z$._-][a-zA-Z0-9$._-]*]]: vector<f32>) -> vector<3x2xf32> {
// CHECK: %[[VAL_1:.*]] = builtin.unrealized_conversion_cast %[[VAL_0]] : vector<f32> to vector<1xf32>
// CHECK: %[[VAL_2:.*]] = ub.poison : vector<3x2xf32>
// CHECK: %[[VAL_3:.*]] = builtin.unrealized_conversion_cast %[[VAL_2]] : vector<3x2xf32> to !llvm.array<3 x vector<2xf32>>
// CHECK: %[[VAL_4:.*]] = llvm.mlir.constant(0 : index) : i32
// CHECK: %[[VAL_5:.*]] = llvm.extractelement %[[VAL_1]]{{\[}}%[[VAL_4]] : i32] : vector<1xf32>
// CHECK: %[[VAL_6:.*]] = llvm.mlir.poison : vector<2xf32>
// CHECK: %[[VAL_7:.*]] = llvm.mlir.constant(0 : i32) : i32
// CHECK: %[[VAL_8:.*]] = llvm.insertelement %[[VAL_5]], %[[VAL_6]]{{\[}}%[[VAL_7]] : i32] : vector<2xf32>
// CHECK: %[[VAL_9:.*]] = llvm.shufflevector %[[VAL_8]], %[[VAL_6]] [0, 0] : vector<2xf32>
// CHECK: %[[VAL_10:.*]] = llvm.insertvalue %[[VAL_9]], %[[VAL_3]][0] : !llvm.array<3 x vector<2xf32>>
// CHECK: %[[VAL_11:.*]] = llvm.insertvalue %[[VAL_9]], %[[VAL_10]][1] : !llvm.array<3 x vector<2xf32>>
// CHECK: %[[VAL_12:.*]] = llvm.insertvalue %[[VAL_9]], %[[VAL_11]][2] : !llvm.array<3 x vector<2xf32>>
// CHECK: %[[VAL_13:.*]] = builtin.unrealized_conversion_cast %[[VAL_12]] : !llvm.array<3 x vector<2xf32>> to vector<3x2xf32>
// CHECK: return %[[VAL_13]] : vector<3x2xf32>
// CHECK: }
func.func @broadcast_vec2d_from_vec0d(%arg0: vector<f32>) -> vector<3x2xf32> {
%0 = vector.broadcast %arg0 : vector<f32> to vector<3x2xf32>
return %0 : vector<3x2xf32>
}
}
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