Skip to content
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
24 changes: 20 additions & 4 deletions llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -13963,15 +13963,31 @@ InstructionCost BoUpSLP::getGatherCost(ArrayRef<Value *> VL, bool ForPoisonSrc,
ShuffledElements.setBit(I);
ShuffleMask[I] = Res.first->second;
}
if (!DemandedElements.isZero())
Cost +=
TTI->getScalarizationOverhead(VecTy, DemandedElements, /*Insert=*/true,
/*Extract=*/false, CostKind, VL);
if (!DemandedElements.isZero()) {
if (isa<FixedVectorType>(ScalarTy)) {
assert(SLPReVec && "Only supported by REVEC.");
// We don't need to insert elements one by one. Instead, we can insert the
// entire vector into the destination.
Cost = 0;
unsigned ScalarTyNumElements = getNumElements(ScalarTy);
for (unsigned I : seq<unsigned>(VL.size()))
if (DemandedElements[I])
Cost += ::getShuffleCost(*TTI, TTI::SK_InsertSubvector, VecTy, {},
CostKind, I * ScalarTyNumElements,
cast<FixedVectorType>(ScalarTy));
} else {
Cost += TTI->getScalarizationOverhead(VecTy, DemandedElements,
/*Insert=*/true,
/*Extract=*/false, CostKind, VL);
}
}
if (ForPoisonSrc) {
if (isa<FixedVectorType>(ScalarTy)) {
assert(SLPReVec && "Only supported by REVEC.");
// We don't need to insert elements one by one. Instead, we can insert the
// entire vector into the destination.
assert(DemandedElements.isZero() &&
"Need to consider the cost from DemandedElements.");
Cost = 0;
unsigned ScalarTyNumElements = getNumElements(ScalarTy);
for (unsigned I : seq<unsigned>(VL.size()))
Expand Down
45 changes: 45 additions & 0 deletions llvm/test/Transforms/SLPVectorizer/SystemZ/revec-fix-128169.ll
Original file line number Diff line number Diff line change
@@ -0,0 +1,45 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -mtriple=s390x-unknown-linux-gnu -mcpu=arch15 -passes=slp-vectorizer -S -slp-revec %s | FileCheck %s

define void @e(<4 x i16> %0) {
; CHECK-LABEL: @e(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i16> [ zeroinitializer, [[ENTRY:%.*]] ], [ zeroinitializer, [[VECTOR_BODY]] ]
; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[ENTRY]] ], [ [[TMP12:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i16> [[VEC_IND]], zeroinitializer
; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32>
; CHECK-NEXT: [[TMP3:%.*]] = add <4 x i16> [[VEC_IND]], zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = icmp sgt <4 x i16> [[TMP0:%.*]], zeroinitializer
; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i1> [[TMP4]] to <4 x i32>
; CHECK-NEXT: [[TMP6:%.*]] = or <4 x i32> [[TMP2]], [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = icmp sgt <4 x i16> [[TMP3]], zeroinitializer
; CHECK-NEXT: [[TMP8:%.*]] = zext <4 x i1> [[TMP7]] to <4 x i32>
; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i32> [[TMP6]], [[TMP8]]
; CHECK-NEXT: [[TMP10:%.*]] = icmp sgt <4 x i16> zeroinitializer, zeroinitializer
; CHECK-NEXT: [[TMP11:%.*]] = zext <4 x i1> [[TMP10]] to <4 x i32>
; CHECK-NEXT: [[TMP12]] = or <4 x i32> [[TMP9]], [[TMP11]]
; CHECK-NEXT: br label [[VECTOR_BODY]]
;
entry:
br label %vector.body

vector.body: ; preds = %vector.body, %entry
%vec.ind = phi <4 x i16> [ zeroinitializer, %entry ], [ zeroinitializer, %vector.body ]
%vec.phi = phi <4 x i32> [ zeroinitializer, %entry ], [ %13, %vector.body ]
%1 = icmp sgt <4 x i16> %vec.ind, zeroinitializer
%2 = zext <4 x i1> %1 to <4 x i32>
%3 = add <4 x i16> %vec.ind, zeroinitializer
%4 = icmp sgt <4 x i16> %0, zeroinitializer
%5 = zext <4 x i1> %4 to <4 x i32>
%6 = or <4 x i32> %2, %5
%7 = add <4 x i16> zeroinitializer, zeroinitializer
%8 = icmp sgt <4 x i16> %3, zeroinitializer
%9 = zext <4 x i1> %8 to <4 x i32>
%10 = or <4 x i32> %6, %9
%11 = icmp sgt <4 x i16> %7, zeroinitializer
%12 = zext <4 x i1> %11 to <4 x i32>
%13 = or <4 x i32> %10, %12
br label %vector.body
}
Loading