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[RISCV] Update MicroOpBufferSize in P400 & P600 scheduling models #128786

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Merged
merged 1 commit into from
Feb 26, 2025
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[RISCV] Update MicroOpBufferSize in P400 & P600 scheduling models #128786

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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
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Expand Up @@ -119,7 +119,7 @@ class SiFiveP400VSM3CCycles<string mx> {

def SiFiveP400Model : SchedMachineModel {
let IssueWidth = 3; // 3 micro-ops are dispatched per cycle.
let MicroOpBufferSize = 56; // Max micro-ops that can be buffered.
let MicroOpBufferSize = 96; // Max micro-ops that can be buffered.
let LoadLatency = 4; // Cycles for loads to access the cache.
let MispredictPenalty = 9; // Extra cycles for a mispredicted branch.
let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
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8 changes: 4 additions & 4 deletions llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td
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Expand Up @@ -286,10 +286,10 @@ class SiFiveP600VSHA2MSCycles<string mx, int sew> {

// SiFiveP600 machine model for scheduling and other instruction cost heuristics.
def SiFiveP600Model : SchedMachineModel {
let IssueWidth = 4; // 4 micro-ops are dispatched per cycle.
let MicroOpBufferSize = 160; // Max micro-ops that can be buffered.
let LoadLatency = 4; // Cycles for loads to access the cache.
let MispredictPenalty = 9; // Extra cycles for a mispredicted branch.
let IssueWidth = 4; // 4 micro-ops are dispatched per cycle.
let MicroOpBufferSize = 192; // Max micro-ops that can be buffered.
let LoadLatency = 4; // Cycles for loads to access the cache.
let MispredictPenalty = 9; // Extra cycles for a mispredicted branch.
let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
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6 changes: 3 additions & 3 deletions llvm/test/tools/llvm-mca/RISCV/SiFiveP400/div.s
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Expand Up @@ -328,12 +328,12 @@ vfsqrt.v v8, v16

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 320
# CHECK-NEXT: Total Cycles: 22358
# CHECK-NEXT: Total Cycles: 19388
# CHECK-NEXT: Total uOps: 320

# CHECK: Dispatch Width: 3
# CHECK-NEXT: uOps Per Cycle: 0.01
# CHECK-NEXT: IPC: 0.01
# CHECK-NEXT: uOps Per Cycle: 0.02
# CHECK-NEXT: IPC: 0.02
# CHECK-NEXT: Block RThroughput: 14361.0

# CHECK: Instruction Info:
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2 changes: 1 addition & 1 deletion llvm/test/tools/llvm-mca/RISCV/SiFiveP400/vlseg-vsseg.s
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Expand Up @@ -1606,7 +1606,7 @@ vsoxseg8ei64.v v8, (a0), v16

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 1540
# CHECK-NEXT: Total Cycles: 29967
# CHECK-NEXT: Total Cycles: 28335
# CHECK-NEXT: Total uOps: 1540

# CHECK: Dispatch Width: 3
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2 changes: 1 addition & 1 deletion llvm/test/tools/llvm-mca/RISCV/SiFiveP600/div.s
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Expand Up @@ -328,7 +328,7 @@ vfsqrt.v v8, v16

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 320
# CHECK-NEXT: Total Cycles: 14613
# CHECK-NEXT: Total Cycles: 14397
# CHECK-NEXT: Total uOps: 320

# CHECK: Dispatch Width: 4
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