Skip to content

[SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} #128800

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 5 commits into from
Feb 28, 2025
Merged

[SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM} #128800

Show file tree
Hide file tree
Changes from 2 commits
Commits
Show all changes
5 commits
Select commit Hold shift + click to select a range
50cc58c
[SelectionDAG][RISCV] Promote VECREDUCE_{FMAX,FMIN,FMAXIMUM,FMINIMUM}
tclin914 Feb 24, 2025
496b064
clang-format
tclin914 Feb 26, 2025
e43532f
prmote -> promote
tclin914 Feb 26, 2025
2319dde
Add tests for bf16/zvfbfmin
tclin914 Feb 27, 2025
d1cff55
nxv4f16 -> nxv4bf16 for bf16 tests
tclin914 Feb 28, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
25 changes: 18 additions & 7 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2913,31 +2913,34 @@ SDValue SelectionDAGLegalize::ExpandPARITY(SDValue Op, const SDLoc &dl) {
}

SDValue SelectionDAGLegalize::PromoteReduction(SDNode *Node) {
MVT VecVT = Node->getOperand(1).getSimpleValueType();
bool IsVPOpcode = ISD::isVPOpcode(Node->getOpcode());
MVT VecVT = IsVPOpcode ? Node->getOperand(1).getSimpleValueType()
: Node->getOperand(0).getSimpleValueType();
MVT NewVecVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VecVT);
MVT ScalarVT = Node->getSimpleValueType(0);
MVT NewScalarVT = NewVecVT.getVectorElementType();

SDLoc DL(Node);
SmallVector<SDValue, 4> Operands(Node->getNumOperands());

// promote the initial value.
// FIXME: Support integer.
assert(Node->getOperand(0).getValueType().isFloatingPoint() &&
"Only FP promotion is supported");
Operands[0] =
DAG.getNode(ISD::FP_EXTEND, DL, NewScalarVT, Node->getOperand(0));

for (unsigned j = 1; j != Node->getNumOperands(); ++j)
for (unsigned j = 0; j != Node->getNumOperands(); ++j)
if (Node->getOperand(j).getValueType().isVector() &&
!(ISD::isVPOpcode(Node->getOpcode()) &&
!(IsVPOpcode &&
ISD::getVPMaskIdx(Node->getOpcode()) == j)) { // Skip mask operand.
// promote the vector operand.
// FIXME: Support integer.
assert(Node->getOperand(j).getValueType().isFloatingPoint() &&
"Only FP promotion is supported");
Operands[j] =
DAG.getNode(ISD::FP_EXTEND, DL, NewVecVT, Node->getOperand(j));
} else if (Node->getOperand(j).getValueType().isFloatingPoint()) {
// prmote the initial value.
Operands[j] =
DAG.getNode(ISD::FP_EXTEND, DL, NewScalarVT, Node->getOperand(j));
} else {
Operands[j] = Node->getOperand(j); // Skip VL operand.
}
Expand Down Expand Up @@ -5049,7 +5052,11 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
Node->getOpcode() == ISD::SINT_TO_FP ||
Node->getOpcode() == ISD::SETCC ||
Node->getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
Node->getOpcode() == ISD::INSERT_VECTOR_ELT) {
Node->getOpcode() == ISD::INSERT_VECTOR_ELT ||
Node->getOpcode() == ISD::VECREDUCE_FMAX ||
Node->getOpcode() == ISD::VECREDUCE_FMIN ||
Node->getOpcode() == ISD::VECREDUCE_FMAXIMUM ||
Node->getOpcode() == ISD::VECREDUCE_FMINIMUM) {
OVT = Node->getOperand(0).getSimpleValueType();
}
if (Node->getOpcode() == ISD::ATOMIC_STORE ||
Expand Down Expand Up @@ -5796,6 +5803,10 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
DAG.getIntPtrConstant(0, dl, /*isTarget=*/true)));
break;
}
case ISD::VECREDUCE_FMAX:
case ISD::VECREDUCE_FMIN:
case ISD::VECREDUCE_FMAXIMUM:
case ISD::VECREDUCE_FMINIMUM:
case ISD::VP_REDUCE_FMAX:
case ISD::VP_REDUCE_FMIN:
case ISD::VP_REDUCE_FMAXIMUM:
Expand Down
8 changes: 7 additions & 1 deletion llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -503,13 +503,19 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
case ISD::VECREDUCE_UMIN:
case ISD::VECREDUCE_FADD:
case ISD::VECREDUCE_FMUL:
case ISD::VECTOR_FIND_LAST_ACTIVE:
Action = TLI.getOperationAction(Node->getOpcode(),
Node->getOperand(0).getValueType());
break;
case ISD::VECREDUCE_FMAX:
case ISD::VECREDUCE_FMIN:
case ISD::VECREDUCE_FMAXIMUM:
case ISD::VECREDUCE_FMINIMUM:
case ISD::VECTOR_FIND_LAST_ACTIVE:
Action = TLI.getOperationAction(Node->getOpcode(),
Node->getOperand(0).getValueType());
// Defer non-vector results to LegalizeDAG.
if (Action == TargetLowering::Promote)
Action = TargetLowering::Legal;
break;
case ISD::VECREDUCE_SEQ_FADD:
case ISD::VECREDUCE_SEQ_FMUL:
Expand Down
36 changes: 29 additions & 7 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -959,13 +959,35 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,

// TODO: support more ops.
static const unsigned ZvfhminZvfbfminPromoteOps[] = {
ISD::FMINNUM, ISD::FMAXNUM, ISD::FADD, ISD::FSUB,
ISD::FMUL, ISD::FMA, ISD::FDIV, ISD::FSQRT,
ISD::FCEIL, ISD::FTRUNC, ISD::FFLOOR, ISD::FROUND,
ISD::FROUNDEVEN, ISD::FRINT, ISD::FNEARBYINT, ISD::IS_FPCLASS,
ISD::SETCC, ISD::FMAXIMUM, ISD::FMINIMUM, ISD::STRICT_FADD,
ISD::STRICT_FSUB, ISD::STRICT_FMUL, ISD::STRICT_FDIV, ISD::STRICT_FSQRT,
ISD::STRICT_FMA};
ISD::FMINNUM,
ISD::FMAXNUM,
ISD::FADD,
ISD::FSUB,
ISD::FMUL,
ISD::FMA,
ISD::FDIV,
ISD::FSQRT,
ISD::FCEIL,
ISD::FTRUNC,
ISD::FFLOOR,
ISD::FROUND,
ISD::FROUNDEVEN,
ISD::FRINT,
ISD::FNEARBYINT,
ISD::IS_FPCLASS,
ISD::SETCC,
ISD::FMAXIMUM,
ISD::FMINIMUM,
ISD::STRICT_FADD,
ISD::STRICT_FSUB,
ISD::STRICT_FMUL,
ISD::STRICT_FDIV,
ISD::STRICT_FSQRT,
ISD::STRICT_FMA,
ISD::VECREDUCE_FMIN,
ISD::VECREDUCE_FMAX,
ISD::VECREDUCE_FMINIMUM,
ISD::VECREDUCE_FMAXIMUM};

// TODO: support more vp ops.
static const unsigned ZvfhminZvfbfminPromoteVPOps[] = {
Expand Down
212 changes: 212 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode-f16.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,212 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVFH
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVFH
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVFHMIN
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=ZVFHMIN

define half @vreduce_fmin_nxv4f16(<vscale x 4 x half> %val) {
; ZVFH-LABEL: vreduce_fmin_nxv4f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFH-NEXT: vfredmin.vs v8, v8, v8
; ZVFH-NEXT: vfmv.f.s fa0, v8
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vreduce_fmin_nxv4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfredmin.vs v8, v10, v10
; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
; ZVFHMIN-NEXT: ret
%s = call half @llvm.vector.reduce.fmin.nxv4f16(<vscale x 4 x half> %val)
ret half %s
}

define half @vreduce_fmax_nxv4f16(<vscale x 4 x half> %val) {
; ZVFH-LABEL: vreduce_fmax_nxv4f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFH-NEXT: vfredmax.vs v8, v8, v8
; ZVFH-NEXT: vfmv.f.s fa0, v8
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vreduce_fmax_nxv4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfredmax.vs v8, v10, v10
; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
; ZVFHMIN-NEXT: ret
%s = call half @llvm.vector.reduce.fmax.nxv4f16(<vscale x 4 x half> %val)
ret half %s
}

define half @vreduce_fmin_nnan_nxv4f16(<vscale x 4 x half> %val) {
; ZVFH-LABEL: vreduce_fmin_nnan_nxv4f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFH-NEXT: vfredmin.vs v8, v8, v8
; ZVFH-NEXT: vfmv.f.s fa0, v8
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vreduce_fmin_nnan_nxv4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfredmin.vs v8, v10, v10
; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
; ZVFHMIN-NEXT: ret
%s = call nnan half @llvm.vector.reduce.fmin.nxv4f16(<vscale x 4 x half> %val)
ret half %s
}

define half @vreduce_fmax_nnan_nxv4f16(<vscale x 4 x half> %val) {
; ZVFH-LABEL: vreduce_fmax_nnan_nxv4f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFH-NEXT: vfredmax.vs v8, v8, v8
; ZVFH-NEXT: vfmv.f.s fa0, v8
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vreduce_fmax_nnan_nxv4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfredmax.vs v8, v10, v10
; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
; ZVFHMIN-NEXT: ret
%s = call nnan half @llvm.vector.reduce.fmax.nxv4f16(<vscale x 4 x half> %val)
ret half %s
}

define half @vreduce_fminimum_nxv4f16(<vscale x 4 x half> %val) {
; ZVFH-LABEL: vreduce_fminimum_nxv4f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFH-NEXT: vmfne.vv v9, v8, v8
; ZVFH-NEXT: vcpop.m a0, v9
; ZVFH-NEXT: beqz a0, .LBB4_2
; ZVFH-NEXT: # %bb.1:
; ZVFH-NEXT: lui a0, %hi(.LCPI4_0)
; ZVFH-NEXT: flh fa0, %lo(.LCPI4_0)(a0)
; ZVFH-NEXT: ret
; ZVFH-NEXT: .LBB4_2:
; ZVFH-NEXT: vfredmin.vs v8, v8, v8
; ZVFH-NEXT: vfmv.f.s fa0, v8
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vreduce_fminimum_nxv4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vmfne.vv v8, v10, v10
; ZVFHMIN-NEXT: vcpop.m a0, v8
; ZVFHMIN-NEXT: beqz a0, .LBB4_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: lui a0, 523264
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
; ZVFHMIN-NEXT: ret
; ZVFHMIN-NEXT: .LBB4_2:
; ZVFHMIN-NEXT: vfredmin.vs v8, v10, v10
; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
; ZVFHMIN-NEXT: ret
%s = call half @llvm.vector.reduce.fminimum.nxv4f16(<vscale x 4 x half> %val)
ret half %s
}

define half @vreduce_fmaximum_nxv4f16(<vscale x 4 x half> %val) {
; ZVFH-LABEL: vreduce_fmaximum_nxv4f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFH-NEXT: vmfne.vv v9, v8, v8
; ZVFH-NEXT: vcpop.m a0, v9
; ZVFH-NEXT: beqz a0, .LBB5_2
; ZVFH-NEXT: # %bb.1:
; ZVFH-NEXT: lui a0, %hi(.LCPI5_0)
; ZVFH-NEXT: flh fa0, %lo(.LCPI5_0)(a0)
; ZVFH-NEXT: ret
; ZVFH-NEXT: .LBB5_2:
; ZVFH-NEXT: vfredmax.vs v8, v8, v8
; ZVFH-NEXT: vfmv.f.s fa0, v8
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vreduce_fmaximum_nxv4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vmfne.vv v8, v10, v10
; ZVFHMIN-NEXT: vcpop.m a0, v8
; ZVFHMIN-NEXT: beqz a0, .LBB5_2
; ZVFHMIN-NEXT: # %bb.1:
; ZVFHMIN-NEXT: lui a0, 523264
; ZVFHMIN-NEXT: fmv.w.x fa5, a0
; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
; ZVFHMIN-NEXT: ret
; ZVFHMIN-NEXT: .LBB5_2:
; ZVFHMIN-NEXT: vfredmax.vs v8, v10, v10
; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
; ZVFHMIN-NEXT: ret
%s = call half @llvm.vector.reduce.fmaximum.nxv4f16(<vscale x 4 x half> %val)
ret half %s
}

define half @vreduce_fminimum_nnan_nxv4f16(<vscale x 4 x half> %val) {
; ZVFH-LABEL: vreduce_fminimum_nnan_nxv4f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFH-NEXT: vfredmin.vs v8, v8, v8
; ZVFH-NEXT: vfmv.f.s fa0, v8
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vreduce_fminimum_nnan_nxv4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfredmin.vs v8, v10, v10
; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
; ZVFHMIN-NEXT: ret
%s = call nnan half @llvm.vector.reduce.fminimum.nxv4f16(<vscale x 4 x half> %val)
ret half %s
}

define half @vreduce_fmaximum_nnan_nxv4f16(<vscale x 4 x half> %val) {
; ZVFH-LABEL: vreduce_fmaximum_nnan_nxv4f16:
; ZVFH: # %bb.0:
; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFH-NEXT: vfredmax.vs v8, v8, v8
; ZVFH-NEXT: vfmv.f.s fa0, v8
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vreduce_fmaximum_nnan_nxv4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v10, v8
; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; ZVFHMIN-NEXT: vfredmax.vs v8, v10, v10
; ZVFHMIN-NEXT: vfmv.f.s fa5, v8
; ZVFHMIN-NEXT: fcvt.h.s fa0, fa5
; ZVFHMIN-NEXT: ret
%s = call nnan half @llvm.vector.reduce.fmaximum.nxv4f16(<vscale x 4 x half> %val)
ret half %s
}

Loading
Loading