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[RISCV] Xqccmp Code Generation #128815

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Merged
merged 22 commits into from
Mar 5, 2025
Merged

[RISCV] Xqccmp Code Generation #128815

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6f8c6d1
[RISCV] Add Xqccmp Assembly Support
lenary Feb 25, 2025
1d71256
fixup! [RISCV] Add Xqccmp Assembly Support
lenary Feb 25, 2025
8162983
fixup! [RISCV] Add Xqccmp Assembly Support
lenary Feb 25, 2025
7e13372
fixup! [RISCV] Add Xqccmp Assembly Support
lenary Feb 25, 2025
b33add5
fixup! [RISCV] Add Xqccmp Assembly Support
lenary Feb 25, 2025
47e63a8
fixup! [RISCV] Add Xqccmp Assembly Support
lenary Feb 25, 2025
9e24cf9
[RISCV] Xqccmp Code Generation
lenary Feb 25, 2025
890cd31
Merge remote-tracking branch 'origin/main' into pr/xqccmp-assembly
lenary Feb 26, 2025
009a1cb
fixup! [RISCV] Add Xqccmp Assembly Support
lenary Feb 26, 2025
03a80db
Merge branch 'pr/xqccmp-assembly' into pr/riscv-xqccmp-codegen
lenary Feb 26, 2025
a80217e
fixup! [RISCV] Xqccmp Code Generation
lenary Feb 26, 2025
ee4b3c6
fixup! [RISCV] Xqccmp Code Generation
lenary Feb 26, 2025
607d6f4
fixup! [RISCV] Add Xqccmp Assembly Support
lenary Feb 26, 2025
cd9d4e3
Merge remote-tracking branch 'origin/main' into pr/xqccmp-assembly
lenary Feb 26, 2025
5d45bc7
Merge branch 'pr/xqccmp-assembly' into pr/riscv-xqccmp-codegen
lenary Feb 26, 2025
b5aa9bb
fixup! [RISCV] Xqccmp Code Generation
lenary Feb 26, 2025
35800f2
Merge remote-tracking branch 'origin/main' into pr/riscv-xqccmp-codegen
lenary Feb 28, 2025
ee917b4
Emit CFI to FP but don't move FP
lenary Feb 28, 2025
69eae06
fixup! Emit CFI to FP but don't move FP
lenary Feb 28, 2025
7eaab5f
fixup! Emit CFI to FP but don't move FP
lenary Feb 28, 2025
cbcf190
Merge remote-tracking branch 'origin/main' into pr/riscv-xqccmp-codegen
lenary Mar 4, 2025
c34be29
Fix Xqccmp test interrupt attributes
lenary Mar 4, 2025
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13 changes: 8 additions & 5 deletions llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -974,17 +974,20 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
emitCFIForCSI<CFISaveRegisterEmitter>(MBB, MBBI, getUnmanagedCSI(MF, CSI));

// Generate new FP.
if (hasFP(MF) && RVFI->getPushPopKind(MF) !=
RISCVMachineFunctionInfo::PushPopKind::VendorXqccmp) {
if (hasFP(MF)) {
if (STI.isRegisterReservedByUser(FPReg))
MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{
MF.getFunction(), "Frame pointer required, but has been reserved."});
// The frame pointer does need to be reserved from register allocation.
assert(MF.getRegInfo().isReserved(FPReg) && "FP not reserved");

RI->adjustReg(MBB, MBBI, DL, FPReg, SPReg,
StackOffset::getFixed(RealStackSize - RVFI->getVarArgsSaveSize()),
MachineInstr::FrameSetup, getStackAlign());
// Xqxxmp with hasFP will update FP using `qc.cm.pushfp`, so we don't need
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@topperc topperc Feb 28, 2025

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Xqccmp*

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@lenary lenary Feb 28, 2025

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Thanks, sorted.

// to update it again, but we do need to emit the `.cfi_def_cfa` below.
if (RVFI->getPushPopKind(MF) != RISCVMachineFunctionInfo::PushPopKind::VendorXqccmp) {
RI->adjustReg(MBB, MBBI, DL, FPReg, SPReg,
StackOffset::getFixed(RealStackSize - RVFI->getVarArgsSaveSize()),
MachineInstr::FrameSetup, getStackAlign());
}

// Emit ".cfi_def_cfa $fp, RVFI->getVarArgsSaveSize()"
unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
Expand Down
8 changes: 8 additions & 0 deletions llvm/test/CodeGen/RISCV/xqccmp-callee-saved-gprs.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -128,6 +128,7 @@ define void @callee() {
; RV32IXQCCMP-WITH-FP-NEXT: .cfi_offset s9, -44
; RV32IXQCCMP-WITH-FP-NEXT: .cfi_offset s10, -48
; RV32IXQCCMP-WITH-FP-NEXT: .cfi_offset s11, -52
; RV32IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa s0, 0
; RV32IXQCCMP-WITH-FP-NEXT: lui t1, %hi(var)
; RV32IXQCCMP-WITH-FP-NEXT: lw a0, %lo(var)(t1)
; RV32IXQCCMP-WITH-FP-NEXT: sw a0, -56(s0) # 4-byte Folded Spill
Expand Down Expand Up @@ -325,6 +326,7 @@ define void @callee() {
; RV64IXQCCMP-WITH-FP-NEXT: .cfi_offset s9, -88
; RV64IXQCCMP-WITH-FP-NEXT: .cfi_offset s10, -96
; RV64IXQCCMP-WITH-FP-NEXT: .cfi_offset s11, -104
; RV64IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa s0, 0
; RV64IXQCCMP-WITH-FP-NEXT: lui t1, %hi(var)
; RV64IXQCCMP-WITH-FP-NEXT: lw a0, %lo(var)(t1)
; RV64IXQCCMP-WITH-FP-NEXT: sd a0, -112(s0) # 8-byte Folded Spill
Expand Down Expand Up @@ -569,6 +571,7 @@ define void @caller() {
; RV32IXQCCMP-WITH-FP-NEXT: .cfi_offset s11, -52
; RV32IXQCCMP-WITH-FP-NEXT: addi sp, sp, -32
; RV32IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa_offset 144
; RV32IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa s0, 0
; RV32IXQCCMP-WITH-FP-NEXT: lui s6, %hi(var)
; RV32IXQCCMP-WITH-FP-NEXT: lw a0, %lo(var)(s6)
; RV32IXQCCMP-WITH-FP-NEXT: sw a0, -56(s0) # 4-byte Folded Spill
Expand Down Expand Up @@ -840,6 +843,7 @@ define void @caller() {
; RV64IXQCCMP-WITH-FP-NEXT: .cfi_offset s11, -104
; RV64IXQCCMP-WITH-FP-NEXT: addi sp, sp, -128
; RV64IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa_offset 288
; RV64IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa s0, 0
; RV64IXQCCMP-WITH-FP-NEXT: lui s6, %hi(var)
; RV64IXQCCMP-WITH-FP-NEXT: lw a0, %lo(var)(s6)
; RV64IXQCCMP-WITH-FP-NEXT: sd a0, -112(s0) # 8-byte Folded Spill
Expand Down Expand Up @@ -983,6 +987,7 @@ define void @foo() {
; RV32IXQCCMP-WITH-FP-NEXT: .cfi_offset ra, -4
; RV32IXQCCMP-WITH-FP-NEXT: .cfi_offset s0, -8
; RV32IXQCCMP-WITH-FP-NEXT: .cfi_offset s4, -24
; RV32IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa s0, 0
; RV32IXQCCMP-WITH-FP-NEXT: #APP
; RV32IXQCCMP-WITH-FP-NEXT: li s4, 0
; RV32IXQCCMP-WITH-FP-NEXT: #NO_APP
Expand All @@ -1006,6 +1011,7 @@ define void @foo() {
; RV64IXQCCMP-WITH-FP-NEXT: .cfi_offset ra, -8
; RV64IXQCCMP-WITH-FP-NEXT: .cfi_offset s0, -16
; RV64IXQCCMP-WITH-FP-NEXT: .cfi_offset s4, -48
; RV64IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa s0, 0
; RV64IXQCCMP-WITH-FP-NEXT: #APP
; RV64IXQCCMP-WITH-FP-NEXT: li s4, 0
; RV64IXQCCMP-WITH-FP-NEXT: #NO_APP
Expand Down Expand Up @@ -1035,6 +1041,7 @@ define void @bar() {
; RV32IXQCCMP-WITH-FP-NEXT: .cfi_offset ra, -4
; RV32IXQCCMP-WITH-FP-NEXT: .cfi_offset s0, -8
; RV32IXQCCMP-WITH-FP-NEXT: .cfi_offset s11, -52
; RV32IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa s0, 0
; RV32IXQCCMP-WITH-FP-NEXT: #APP
; RV32IXQCCMP-WITH-FP-NEXT: li s11, 0
; RV32IXQCCMP-WITH-FP-NEXT: #NO_APP
Expand All @@ -1058,6 +1065,7 @@ define void @bar() {
; RV64IXQCCMP-WITH-FP-NEXT: .cfi_offset ra, -8
; RV64IXQCCMP-WITH-FP-NEXT: .cfi_offset s0, -16
; RV64IXQCCMP-WITH-FP-NEXT: .cfi_offset s11, -104
; RV64IXQCCMP-WITH-FP-NEXT: .cfi_def_cfa s0, 0
; RV64IXQCCMP-WITH-FP-NEXT: #APP
; RV64IXQCCMP-WITH-FP-NEXT: li s11, 0
; RV64IXQCCMP-WITH-FP-NEXT: #NO_APP
Expand Down
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