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[X86] Merge insertsubvector(load(p0),load_subv(p0),hi) -> subvbroadcast(p0) if either load is oneuse #128857

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Merged
merged 3 commits into from
Feb 27, 2025
Merged

[X86] Merge insertsubvector(load(p0),load_subv(p0),hi) -> subvbroadcast(p0) if either load is oneuse #128857

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[X86] Merge insertsubvector(load(p0),load_subv(p0),hi) -> subvbroadca…
RKSimon Feb 26, 2025
5b93950
Ensure ensure all subvector uses are replaced
RKSimon Feb 26, 2025
f1798e8
Merge branch 'upstream' into x86-insertvector-subvbroadcast-oneuse
RKSimon Feb 26, 2025
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5 changes: 3 additions & 2 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -58562,8 +58562,9 @@ static SDValue combineINSERT_SUBVECTOR(SDNode *N, SelectionDAG &DAG,

// If we're splatting the lower half subvector of a full vector load into the
// upper half, attempt to create a subvector broadcast.
if (IdxVal == (OpVT.getVectorNumElements() / 2) && SubVec.hasOneUse() &&
Vec.getValueSizeInBits() == (2 * SubVec.getValueSizeInBits())) {
if (IdxVal == (OpVT.getVectorNumElements() / 2) &&
Vec.getValueSizeInBits() == (2 * SubVec.getValueSizeInBits()) &&
(Vec.hasOneUse() || SubVec.hasOneUse())) {
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@phoebewang phoebewang Feb 26, 2025

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Does Vec have oneuse matter? Can't the loaded value be used more than once?

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@RKSimon RKSimon Feb 26, 2025

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Let me see if I can get this to always replace uses of subvec - then we can get rid of the oneuse checks entirely

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@RKSimon RKSimon Feb 26, 2025 •
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The oneuse checks are still preventing some regressions due to shouldReduceLoadWidth being so permissive, but I've at least ensured that any other uses of SubVec are replaced now.

auto *VecLd = dyn_cast<LoadSDNode>(Vec);
auto *SubLd = dyn_cast<LoadSDNode>(SubVec);
if (VecLd && SubLd &&
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12 changes: 4 additions & 8 deletions llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
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Expand Up @@ -10210,11 +10210,9 @@ define void @store_i8_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512BW-NEXT: vpshufb %ymm28, %ymm18, %ymm23
; AVX512BW-NEXT: vporq %ymm2, %ymm23, %ymm2
; AVX512BW-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1
; AVX512BW-NEXT: vmovdqa64 (%rdx), %zmm2
; AVX512BW-NEXT: vinserti64x4 $1, %ymm14, %zmm2, %zmm2
; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm2 = mem[0,1,2,3,0,1,2,3]
; AVX512BW-NEXT: vpshufb %zmm20, %zmm2, %zmm2
; AVX512BW-NEXT: vmovdqa64 (%rcx), %zmm20
; AVX512BW-NEXT: vinserti64x4 $1, %ymm15, %zmm20, %zmm20
; AVX512BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm20 = mem[0,1,2,3,0,1,2,3]
; AVX512BW-NEXT: vpshufb %zmm22, %zmm20, %zmm20
; AVX512BW-NEXT: vporq %zmm2, %zmm20, %zmm2
; AVX512BW-NEXT: vpermq {{.*#+}} zmm1 = zmm1[2,3,2,3,6,7,6,7]
Expand Down Expand Up @@ -10816,11 +10814,9 @@ define void @store_i8_stride7_vf64(ptr %in.vecptr0, ptr %in.vecptr1, ptr %in.vec
; AVX512DQ-BW-NEXT: vpshufb %ymm28, %ymm18, %ymm23
; AVX512DQ-BW-NEXT: vporq %ymm2, %ymm23, %ymm2
; AVX512DQ-BW-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1
; AVX512DQ-BW-NEXT: vmovdqa64 (%rdx), %zmm2
; AVX512DQ-BW-NEXT: vinserti64x4 $1, %ymm14, %zmm2, %zmm2
; AVX512DQ-BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm2 = mem[0,1,2,3,0,1,2,3]
; AVX512DQ-BW-NEXT: vpshufb %zmm20, %zmm2, %zmm2
; AVX512DQ-BW-NEXT: vmovdqa64 (%rcx), %zmm20
; AVX512DQ-BW-NEXT: vinserti64x4 $1, %ymm15, %zmm20, %zmm20
; AVX512DQ-BW-NEXT: vbroadcasti64x4 {{.*#+}} zmm20 = mem[0,1,2,3,0,1,2,3]
; AVX512DQ-BW-NEXT: vpshufb %zmm22, %zmm20, %zmm20
; AVX512DQ-BW-NEXT: vporq %zmm2, %zmm20, %zmm2
; AVX512DQ-BW-NEXT: vpermq {{.*#+}} zmm1 = zmm1[2,3,2,3,6,7,6,7]
Expand Down