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[ARM] Use correct ABI for atomic functions #128891

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b2b9dd1
[AArch64] Don't extend arguments to libcalls
ostannard Feb 25, 2025
51a48e3
Re-generate test (whitespace change only)
ostannard Feb 26, 2025
afbfb86
[ARM] Add tests showing missing truncation
ostannard Feb 25, 2025
1bae5be
[ARM] Add signext/zeroext to libcalls in AtomicExpand
ostannard Feb 26, 2025
6135504
[ARM][DAGISel] USe correct ABI for atomic functions
ostannard Feb 26, 2025
f7de953
clang-format
ostannard Feb 26, 2025
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13 changes: 13 additions & 0 deletions llvm/lib/CodeGen/AtomicExpandPass.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1999,6 +1999,19 @@ bool AtomicExpandImpl::expandAtomicOpToLibcall(
Value *IntValue =
Builder.CreateBitOrPointerCast(ValueOperand, SizedIntTy);
Args.push_back(IntValue);

// Set the zeroext/signext attributes on the parameter if needed to match
// the target's ABI.
if (TLI->shouldExtendTypeInLibCall(
TLI->getMemValueType(DL, SizedIntTy))) {
// The only atomic operations affected by signedness are min/max, and
// we don't have __atomic_ libcalls for them, so IsSigned is always
// false.
if (TLI->shouldSignExtendTypeInLibCall(SizedIntTy, false /*IsSigned*/))
Comment on lines +2004 to +2010
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@arsenm arsenm Feb 27, 2025

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This is using 3 levels of terrible TargetLowering API. Really we should be able to query the signature of the specific libcall from RuntimeLibcalls, not these global overrides.

The part I understand least is why you need getMemValueType

Attr = Attr.addParamAttribute(Ctx, Args.size() - 1, Attribute::SExt);
else
Attr = Attr.addParamAttribute(Ctx, Args.size() - 1, Attribute::ZExt);
Comment on lines +2010 to +2013
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@arsenm arsenm Feb 27, 2025

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Suggested change
if (TLI->shouldSignExtendTypeInLibCall(SizedIntTy, false /*IsSigned*/))
Attr = Attr.addParamAttribute(Ctx, Args.size() - 1, Attribute::SExt);
else
Attr = Attr.addParamAttribute(Ctx, Args.size() - 1, Attribute::ZExt);
Attribute::AttrKind ExtAttr = TLI->shouldSignExtendTypeInLibCall(SizedIntTy, /*IsSigned=*/false) ? Attribute::SExt : Attribute::ZExt;
Attr = Attr.addParamAttribute(Ctx, Args.size() - 1, AttrKind);

}
} else {
AllocaValue = AllocaBuilder.CreateAlloca(ValueOperand->getType());
AllocaValue->setAlignment(AllocaAlignment);
Expand Down
37 changes: 30 additions & 7 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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Expand Up @@ -4386,23 +4386,46 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
AtomicOrdering Order = cast<AtomicSDNode>(Node)->getMergedOrdering();
RTLIB::Libcall LC = RTLIB::getOUTLINE_ATOMIC(Opc, Order, VT);
EVT RetVT = Node->getValueType(0);
SDValue ChainIn = Node->getOperand(0);
SDValue Pointer = Node->getOperand(1);
SDLoc dl(Node);
SmallVector<SDValue, 4> Ops;

// Zero/sign extend small operands if required by the target's ABI.
SmallVector<SDValue, 4> ExtendedOps;
for (auto Op = Node->op_begin() + 2, E = Node->op_end(); Op != E; ++Op) {
if (TLI.shouldExtendTypeInLibCall(VT)) {
bool IsSigned =
Opc == ISD::ATOMIC_LOAD_MIN || Opc == ISD::ATOMIC_LOAD_MAX;
if (TLI.shouldSignExtendTypeInLibCall(
EVT(VT).getTypeForEVT(*DAG.getContext()), IsSigned))
ExtendedOps.push_back(DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
Op->getValueType(), *Op,
DAG.getValueType(VT)));
else
ExtendedOps.push_back(DAG.getZeroExtendInReg(*Op, dl, VT));

} else {
ExtendedOps.push_back(*Op);
}
}

if (TLI.getLibcallName(LC)) {
// If outline atomic available, prepare its arguments and expand.
Ops.append(Node->op_begin() + 2, Node->op_end());
Ops.push_back(Node->getOperand(1));
Ops.append(ExtendedOps.begin(), ExtendedOps.end());
Ops.push_back(Pointer);

} else {
LC = RTLIB::getSYNC(Opc, VT);
assert(LC != RTLIB::UNKNOWN_LIBCALL &&
"Unexpected atomic op or value type!");
// Arguments for expansion to sync libcall
Ops.append(Node->op_begin() + 1, Node->op_end());
Ops.push_back(Pointer);
Ops.append(ExtendedOps.begin(), ExtendedOps.end());
}
std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, RetVT,
Ops, CallOptions,
SDLoc(Node),
Node->getOperand(0));

std::pair<SDValue, SDValue> Tmp =
TLI.makeLibCall(DAG, LC, RetVT, Ops, CallOptions, dl, ChainIn);
Results.push_back(Tmp.first);
Results.push_back(Tmp.second);
break;
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1378,6 +1378,8 @@ class AArch64TargetLowering : public TargetLowering {
bool shouldScalarizeBinop(SDValue VecOp) const override {
return VecOp.getOpcode() == ISD::SETCC;
}

bool shouldExtendTypeInLibCall(EVT Type) const override { return false; }
};

namespace AArch64 {
Expand Down
32 changes: 16 additions & 16 deletions llvm/test/CodeGen/AArch64/atomicrmw-fadd.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -58,21 +58,21 @@ define half @test_atomicrmw_fadd_f16_seq_cst_align2(ptr %ptr, half %value) #0 {
; SOFTFP-NOLSE-NEXT: .LBB0_2: // %atomicrmw.start
; SOFTFP-NOLSE-NEXT: // =>This Loop Header: Depth=1
; SOFTFP-NOLSE-NEXT: // Child Loop BB0_3 Depth 2
; SOFTFP-NOLSE-NEXT: mov w22, w0
; SOFTFP-NOLSE-NEXT: and w0, w20, #0xffff
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w21, w0
; SOFTFP-NOLSE-NEXT: and w0, w22, #0xffff
; SOFTFP-NOLSE-NEXT: mov w0, w20
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w1, w21
; SOFTFP-NOLSE-NEXT: mov w22, w0
; SOFTFP-NOLSE-NEXT: mov w0, w21
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w1, w22
; SOFTFP-NOLSE-NEXT: bl __addsf3
; SOFTFP-NOLSE-NEXT: bl __truncsfhf2
; SOFTFP-NOLSE-NEXT: mov w8, w0
; SOFTFP-NOLSE-NEXT: .LBB0_3: // %cmpxchg.start
; SOFTFP-NOLSE-NEXT: // Parent Loop BB0_2 Depth=1
; SOFTFP-NOLSE-NEXT: // => This Inner Loop Header: Depth=2
; SOFTFP-NOLSE-NEXT: ldaxrh w0, [x19]
; SOFTFP-NOLSE-NEXT: cmp w0, w22, uxth
; SOFTFP-NOLSE-NEXT: cmp w0, w21, uxth
; SOFTFP-NOLSE-NEXT: b.ne .LBB0_1
; SOFTFP-NOLSE-NEXT: // %bb.4: // %cmpxchg.trystore
; SOFTFP-NOLSE-NEXT: // in Loop: Header=BB0_3 Depth=2
Expand Down Expand Up @@ -146,21 +146,21 @@ define half @test_atomicrmw_fadd_f16_seq_cst_align4(ptr %ptr, half %value) #0 {
; SOFTFP-NOLSE-NEXT: .LBB1_2: // %atomicrmw.start
; SOFTFP-NOLSE-NEXT: // =>This Loop Header: Depth=1
; SOFTFP-NOLSE-NEXT: // Child Loop BB1_3 Depth 2
; SOFTFP-NOLSE-NEXT: mov w22, w0
; SOFTFP-NOLSE-NEXT: and w0, w20, #0xffff
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w21, w0
; SOFTFP-NOLSE-NEXT: and w0, w22, #0xffff
; SOFTFP-NOLSE-NEXT: mov w0, w20
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w1, w21
; SOFTFP-NOLSE-NEXT: mov w22, w0
; SOFTFP-NOLSE-NEXT: mov w0, w21
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w1, w22
; SOFTFP-NOLSE-NEXT: bl __addsf3
; SOFTFP-NOLSE-NEXT: bl __truncsfhf2
; SOFTFP-NOLSE-NEXT: mov w8, w0
; SOFTFP-NOLSE-NEXT: .LBB1_3: // %cmpxchg.start
; SOFTFP-NOLSE-NEXT: // Parent Loop BB1_2 Depth=1
; SOFTFP-NOLSE-NEXT: // => This Inner Loop Header: Depth=2
; SOFTFP-NOLSE-NEXT: ldaxrh w0, [x19]
; SOFTFP-NOLSE-NEXT: cmp w0, w22, uxth
; SOFTFP-NOLSE-NEXT: cmp w0, w21, uxth
; SOFTFP-NOLSE-NEXT: b.ne .LBB1_1
; SOFTFP-NOLSE-NEXT: // %bb.4: // %cmpxchg.trystore
; SOFTFP-NOLSE-NEXT: // in Loop: Header=BB1_3 Depth=2
Expand Down Expand Up @@ -711,19 +711,19 @@ define <2 x half> @test_atomicrmw_fadd_v2f16_seq_cst_align4(ptr %ptr, <2 x half>
; SOFTFP-NOLSE-NEXT: .LBB7_2: // %atomicrmw.start
; SOFTFP-NOLSE-NEXT: // =>This Loop Header: Depth=1
; SOFTFP-NOLSE-NEXT: // Child Loop BB7_3 Depth 2
; SOFTFP-NOLSE-NEXT: and w0, w19, #0xffff
; SOFTFP-NOLSE-NEXT: mov w0, w19
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w24, w0
; SOFTFP-NOLSE-NEXT: and w0, w23, #0xffff
; SOFTFP-NOLSE-NEXT: mov w0, w23
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w1, w24
; SOFTFP-NOLSE-NEXT: bl __addsf3
; SOFTFP-NOLSE-NEXT: bl __truncsfhf2
; SOFTFP-NOLSE-NEXT: mov w24, w0
; SOFTFP-NOLSE-NEXT: and w0, w21, #0xffff
; SOFTFP-NOLSE-NEXT: mov w0, w21
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w25, w0
; SOFTFP-NOLSE-NEXT: and w0, w22, #0xffff
; SOFTFP-NOLSE-NEXT: mov w0, w22
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w1, w25
; SOFTFP-NOLSE-NEXT: bl __addsf3
Expand Down
32 changes: 16 additions & 16 deletions llvm/test/CodeGen/AArch64/atomicrmw-fmax.ll
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Expand Up @@ -60,21 +60,21 @@ define half @test_atomicrmw_fmax_f16_seq_cst_align2(ptr %ptr, half %value) #0 {
; SOFTFP-NOLSE-NEXT: .LBB0_2: // %atomicrmw.start
; SOFTFP-NOLSE-NEXT: // =>This Loop Header: Depth=1
; SOFTFP-NOLSE-NEXT: // Child Loop BB0_3 Depth 2
; SOFTFP-NOLSE-NEXT: mov w22, w0
; SOFTFP-NOLSE-NEXT: and w0, w20, #0xffff
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w21, w0
; SOFTFP-NOLSE-NEXT: and w0, w22, #0xffff
; SOFTFP-NOLSE-NEXT: mov w0, w20
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w1, w21
; SOFTFP-NOLSE-NEXT: mov w22, w0
; SOFTFP-NOLSE-NEXT: mov w0, w21
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w1, w22
; SOFTFP-NOLSE-NEXT: bl fmaxf
; SOFTFP-NOLSE-NEXT: bl __truncsfhf2
; SOFTFP-NOLSE-NEXT: mov w8, w0
; SOFTFP-NOLSE-NEXT: .LBB0_3: // %cmpxchg.start
; SOFTFP-NOLSE-NEXT: // Parent Loop BB0_2 Depth=1
; SOFTFP-NOLSE-NEXT: // => This Inner Loop Header: Depth=2
; SOFTFP-NOLSE-NEXT: ldaxrh w0, [x19]
; SOFTFP-NOLSE-NEXT: cmp w0, w22, uxth
; SOFTFP-NOLSE-NEXT: cmp w0, w21, uxth
; SOFTFP-NOLSE-NEXT: b.ne .LBB0_1
; SOFTFP-NOLSE-NEXT: // %bb.4: // %cmpxchg.trystore
; SOFTFP-NOLSE-NEXT: // in Loop: Header=BB0_3 Depth=2
Expand Down Expand Up @@ -148,21 +148,21 @@ define half @test_atomicrmw_fmax_f16_seq_cst_align4(ptr %ptr, half %value) #0 {
; SOFTFP-NOLSE-NEXT: .LBB1_2: // %atomicrmw.start
; SOFTFP-NOLSE-NEXT: // =>This Loop Header: Depth=1
; SOFTFP-NOLSE-NEXT: // Child Loop BB1_3 Depth 2
; SOFTFP-NOLSE-NEXT: mov w22, w0
; SOFTFP-NOLSE-NEXT: and w0, w20, #0xffff
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w21, w0
; SOFTFP-NOLSE-NEXT: and w0, w22, #0xffff
; SOFTFP-NOLSE-NEXT: mov w0, w20
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w1, w21
; SOFTFP-NOLSE-NEXT: mov w22, w0
; SOFTFP-NOLSE-NEXT: mov w0, w21
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w1, w22
; SOFTFP-NOLSE-NEXT: bl fmaxf
; SOFTFP-NOLSE-NEXT: bl __truncsfhf2
; SOFTFP-NOLSE-NEXT: mov w8, w0
; SOFTFP-NOLSE-NEXT: .LBB1_3: // %cmpxchg.start
; SOFTFP-NOLSE-NEXT: // Parent Loop BB1_2 Depth=1
; SOFTFP-NOLSE-NEXT: // => This Inner Loop Header: Depth=2
; SOFTFP-NOLSE-NEXT: ldaxrh w0, [x19]
; SOFTFP-NOLSE-NEXT: cmp w0, w22, uxth
; SOFTFP-NOLSE-NEXT: cmp w0, w21, uxth
; SOFTFP-NOLSE-NEXT: b.ne .LBB1_1
; SOFTFP-NOLSE-NEXT: // %bb.4: // %cmpxchg.trystore
; SOFTFP-NOLSE-NEXT: // in Loop: Header=BB1_3 Depth=2
Expand Down Expand Up @@ -591,19 +591,19 @@ define <2 x half> @test_atomicrmw_fmax_v2f16_seq_cst_align4(ptr %ptr, <2 x half>
; SOFTFP-NOLSE-NEXT: .LBB6_2: // %atomicrmw.start
; SOFTFP-NOLSE-NEXT: // =>This Loop Header: Depth=1
; SOFTFP-NOLSE-NEXT: // Child Loop BB6_3 Depth 2
; SOFTFP-NOLSE-NEXT: and w0, w19, #0xffff
; SOFTFP-NOLSE-NEXT: mov w0, w19
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w24, w0
; SOFTFP-NOLSE-NEXT: and w0, w23, #0xffff
; SOFTFP-NOLSE-NEXT: mov w0, w23
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w1, w24
; SOFTFP-NOLSE-NEXT: bl fmaxf
; SOFTFP-NOLSE-NEXT: bl __truncsfhf2
; SOFTFP-NOLSE-NEXT: mov w24, w0
; SOFTFP-NOLSE-NEXT: and w0, w21, #0xffff
; SOFTFP-NOLSE-NEXT: mov w0, w21
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w25, w0
; SOFTFP-NOLSE-NEXT: and w0, w22, #0xffff
; SOFTFP-NOLSE-NEXT: mov w0, w22
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w1, w25
; SOFTFP-NOLSE-NEXT: bl fmaxf
Expand Down
32 changes: 16 additions & 16 deletions llvm/test/CodeGen/AArch64/atomicrmw-fmin.ll
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Expand Up @@ -60,21 +60,21 @@ define half @test_atomicrmw_fmin_f16_seq_cst_align2(ptr %ptr, half %value) #0 {
; SOFTFP-NOLSE-NEXT: .LBB0_2: // %atomicrmw.start
; SOFTFP-NOLSE-NEXT: // =>This Loop Header: Depth=1
; SOFTFP-NOLSE-NEXT: // Child Loop BB0_3 Depth 2
; SOFTFP-NOLSE-NEXT: mov w22, w0
; SOFTFP-NOLSE-NEXT: and w0, w20, #0xffff
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w21, w0
; SOFTFP-NOLSE-NEXT: and w0, w22, #0xffff
; SOFTFP-NOLSE-NEXT: mov w0, w20
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w1, w21
; SOFTFP-NOLSE-NEXT: mov w22, w0
; SOFTFP-NOLSE-NEXT: mov w0, w21
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w1, w22
; SOFTFP-NOLSE-NEXT: bl fminf
; SOFTFP-NOLSE-NEXT: bl __truncsfhf2
; SOFTFP-NOLSE-NEXT: mov w8, w0
; SOFTFP-NOLSE-NEXT: .LBB0_3: // %cmpxchg.start
; SOFTFP-NOLSE-NEXT: // Parent Loop BB0_2 Depth=1
; SOFTFP-NOLSE-NEXT: // => This Inner Loop Header: Depth=2
; SOFTFP-NOLSE-NEXT: ldaxrh w0, [x19]
; SOFTFP-NOLSE-NEXT: cmp w0, w22, uxth
; SOFTFP-NOLSE-NEXT: cmp w0, w21, uxth
; SOFTFP-NOLSE-NEXT: b.ne .LBB0_1
; SOFTFP-NOLSE-NEXT: // %bb.4: // %cmpxchg.trystore
; SOFTFP-NOLSE-NEXT: // in Loop: Header=BB0_3 Depth=2
Expand Down Expand Up @@ -148,21 +148,21 @@ define half @test_atomicrmw_fmin_f16_seq_cst_align4(ptr %ptr, half %value) #0 {
; SOFTFP-NOLSE-NEXT: .LBB1_2: // %atomicrmw.start
; SOFTFP-NOLSE-NEXT: // =>This Loop Header: Depth=1
; SOFTFP-NOLSE-NEXT: // Child Loop BB1_3 Depth 2
; SOFTFP-NOLSE-NEXT: mov w22, w0
; SOFTFP-NOLSE-NEXT: and w0, w20, #0xffff
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w21, w0
; SOFTFP-NOLSE-NEXT: and w0, w22, #0xffff
; SOFTFP-NOLSE-NEXT: mov w0, w20
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w1, w21
; SOFTFP-NOLSE-NEXT: mov w22, w0
; SOFTFP-NOLSE-NEXT: mov w0, w21
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w1, w22
; SOFTFP-NOLSE-NEXT: bl fminf
; SOFTFP-NOLSE-NEXT: bl __truncsfhf2
; SOFTFP-NOLSE-NEXT: mov w8, w0
; SOFTFP-NOLSE-NEXT: .LBB1_3: // %cmpxchg.start
; SOFTFP-NOLSE-NEXT: // Parent Loop BB1_2 Depth=1
; SOFTFP-NOLSE-NEXT: // => This Inner Loop Header: Depth=2
; SOFTFP-NOLSE-NEXT: ldaxrh w0, [x19]
; SOFTFP-NOLSE-NEXT: cmp w0, w22, uxth
; SOFTFP-NOLSE-NEXT: cmp w0, w21, uxth
; SOFTFP-NOLSE-NEXT: b.ne .LBB1_1
; SOFTFP-NOLSE-NEXT: // %bb.4: // %cmpxchg.trystore
; SOFTFP-NOLSE-NEXT: // in Loop: Header=BB1_3 Depth=2
Expand Down Expand Up @@ -591,19 +591,19 @@ define <2 x half> @test_atomicrmw_fmin_v2f16_seq_cst_align4(ptr %ptr, <2 x half>
; SOFTFP-NOLSE-NEXT: .LBB6_2: // %atomicrmw.start
; SOFTFP-NOLSE-NEXT: // =>This Loop Header: Depth=1
; SOFTFP-NOLSE-NEXT: // Child Loop BB6_3 Depth 2
; SOFTFP-NOLSE-NEXT: and w0, w19, #0xffff
; SOFTFP-NOLSE-NEXT: mov w0, w19
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w24, w0
; SOFTFP-NOLSE-NEXT: and w0, w23, #0xffff
; SOFTFP-NOLSE-NEXT: mov w0, w23
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w1, w24
; SOFTFP-NOLSE-NEXT: bl fminf
; SOFTFP-NOLSE-NEXT: bl __truncsfhf2
; SOFTFP-NOLSE-NEXT: mov w24, w0
; SOFTFP-NOLSE-NEXT: and w0, w21, #0xffff
; SOFTFP-NOLSE-NEXT: mov w0, w21
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w25, w0
; SOFTFP-NOLSE-NEXT: and w0, w22, #0xffff
; SOFTFP-NOLSE-NEXT: mov w0, w22
; SOFTFP-NOLSE-NEXT: bl __extendhfsf2
; SOFTFP-NOLSE-NEXT: mov w1, w25
; SOFTFP-NOLSE-NEXT: bl fminf
Expand Down
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