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9 changes: 9 additions & 0 deletions llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -3119,6 +3119,15 @@ static Value *matchOrConcat(Instruction &Or, InstCombiner::BuilderTy &Builder) {
match(UpperSrc, m_BitReverse(m_Value(UpperBRev))))
return ConcatIntrinsicCalls(Intrinsic::bitreverse, UpperBRev, LowerBRev);

Value *X;
if (match(LowerSrc, m_SExt(m_Value(X))) &&
match(UpperSrc,
m_SExt(m_AShr(
m_Specific(X),
m_SpecificInt(X->getType()->getScalarSizeInBits() - 1))))) {
return Builder.CreateSExt(X, Ty);
}

return nullptr;
}

Expand Down
42 changes: 42 additions & 0 deletions llvm/test/Transforms/InstCombine/i128-ext-split.ll
Original file line number Diff line number Diff line change
@@ -0,0 +1,42 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt < %s -passes=instcombine -S | FileCheck %s

; PR129363

define i128 @i128_ext_split(i32 noundef %x) {
; CHECK-LABEL: define i128 @i128_ext_split(
; CHECK-SAME: i32 noundef [[X:%.*]]) {
; CHECK-NEXT: [[XX:%.*]] = sext i32 [[X]] to i128
; CHECK-NEXT: ret i128 [[XX]]
;
%coerce.sroa.0.0.extract.trunc = sext i32 %x to i64
%ashr = ashr i32 %x, 31
%coerce.sroa.2.0.extract.trunc = sext i32 %ashr to i64
%x.sroa.2.0.insert.ext.i = zext i64 %coerce.sroa.2.0.extract.trunc to i128
%x.sroa.2.0.insert.shift.i = shl nuw i128 %x.sroa.2.0.insert.ext.i, 64
%x.sroa.0.0.insert.ext.i = zext i64 %coerce.sroa.0.0.extract.trunc to i128
%x.sroa.0.0.insert.insert.i = or disjoint i128 %x.sroa.2.0.insert.shift.i, %x.sroa.0.0.insert.ext.i
ret i128 %x.sroa.0.0.insert.insert.i
}

define void @i128_ext_split_store(i32 %x, ptr %out) {
; CHECK-LABEL: define void @i128_ext_split_store(
; CHECK-SAME: i32 [[X:%.*]], ptr [[OUT:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[RES:%.*]] = sext i32 [[X]] to i128
; CHECK-NEXT: store i128 [[RES]], ptr [[OUT]], align 16
; CHECK-NEXT: ret void
;
entry:
%LowerSrc = sext i32 %x to i64
%lo = zext i64 %LowerSrc to i128

%sign = ashr i32 %x, 31
%UpperSrc = sext i32 %sign to i64
%widen = zext i64 %UpperSrc to i128
%hi = shl nuw i128 %widen, 64

%res = or disjoint i128 %hi, %lo
store i128 %res, ptr %out, align 16
ret void
}