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[BOLT][AArch64] Refactor ADR to ADRP+ADD conversion pass. NFCI #129399

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Merged
merged 1 commit into from
Mar 1, 2025
Merged

[BOLT][AArch64] Refactor ADR to ADRP+ADD conversion pass. NFCI #129399

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11 changes: 7 additions & 4 deletions bolt/include/bolt/Core/MCPlusBuilder.h
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Original file line number Diff line number Diff line change
Expand Up @@ -637,10 +637,6 @@ class MCPlusBuilder {
return false;
}

virtual void getADRReg(const MCInst &Inst, MCPhysReg &RegName) const {
llvm_unreachable("not implemented");
}

virtual bool isMoveMem2Reg(const MCInst &Inst) const { return false; }

virtual bool mayLoad(const MCInst &Inst) const {
Expand Down Expand Up @@ -1538,6 +1534,13 @@ class MCPlusBuilder {
llvm_unreachable("not implemented");
}

/// Undo the linker's ADRP+ADD to ADR relaxation. Take \p ADRInst and return
/// ADRP+ADD instruction sequence.
virtual InstructionListType undoAdrpAddRelaxation(const MCInst &ADRInst,
MCContext *Ctx) const {
llvm_unreachable("not implemented");
}

/// Return not 0 if the instruction CurInst, in combination with the recent
/// history of disassembled instructions supplied by [Begin, End), is a linker
/// generated veneer/stub that needs patching. This happens in AArch64 when
Expand Down
10 changes: 3 additions & 7 deletions bolt/lib/Passes/ADRRelaxationPass.cpp
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Expand Up @@ -71,14 +71,10 @@ void ADRRelaxationPass::runOnFunction(BinaryFunction &BF) {
continue;
}

MCPhysReg Reg;
BC.MIB->getADRReg(Inst, Reg);
int64_t Addend = BC.MIB->getTargetAddend(Inst);
InstructionListType Addr;

InstructionListType AdrpAdd;
{
auto L = BC.scopeLock();
Addr = BC.MIB->materializeAddress(Symbol, BC.Ctx.get(), Reg, Addend);
AdrpAdd = BC.MIB->undoAdrpAddRelaxation(Inst, BC.Ctx.get());
}

if (It != BB.begin() && BC.MIB->isNoop(*std::prev(It))) {
Expand All @@ -99,7 +95,7 @@ void ADRRelaxationPass::runOnFunction(BinaryFunction &BF) {
PassFailed = true;
return;
}
It = BB.replaceInstruction(It, Addr);
It = BB.replaceInstruction(It, AdrpAdd);
}
}
}
Expand Down
14 changes: 12 additions & 2 deletions bolt/lib/Target/AArch64/AArch64MCPlusBuilder.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -278,13 +278,23 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
return Inst.getOpcode() == AArch64::ADDXri;
}

void getADRReg(const MCInst &Inst, MCPhysReg &RegName) const override {
MCPhysReg getADRReg(const MCInst &Inst) const {
assert((isADR(Inst) || isADRP(Inst)) && "Not an ADR instruction");
assert(MCPlus::getNumPrimeOperands(Inst) != 0 &&
"No operands for ADR instruction");
assert(Inst.getOperand(0).isReg() &&
"Unexpected operand in ADR instruction");
RegName = Inst.getOperand(0).getReg();
return Inst.getOperand(0).getReg();
}

InstructionListType undoAdrpAddRelaxation(const MCInst &ADRInst,
MCContext *Ctx) const override {
assert(isADR(ADRInst) && "ADR instruction expected");

const MCPhysReg Reg = getADRReg(ADRInst);
const MCSymbol *Target = getTargetSymbol(ADRInst);
const uint64_t Addend = getTargetAddend(ADRInst);
return materializeAddress(Target, Ctx, Reg, Addend);
}

bool isTB(const MCInst &Inst) const {
Expand Down
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