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[X86] Remove redundant test after setzucc #129506

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Merged
merged 1 commit into from
Mar 3, 2025
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[X86] Remove redundant test after setzucc #129506

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25 changes: 24 additions & 1 deletion llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -615,7 +615,7 @@ bool X86FlagsCopyLoweringPass::runOnMachineFunction(MachineFunction &MF) {
MRI->replaceRegWith(MI.getOperand(0).getReg(),
CopyDefI.getOperand(0).getReg());
MI.eraseFromParent();
} else if (X86::isSETCC(Opc)) {
} else if (X86::isSETCC(Opc) || X86::isSETZUCC(Opc)) {
rewriteSetCC(*TestMBB, TestPos, TestLoc, MI, CondRegs);
} else if (isArithmeticOp(Opc)) {
rewriteArithmetic(*TestMBB, TestPos, TestLoc, MI, CondRegs);
Expand Down Expand Up @@ -781,6 +781,29 @@ void X86FlagsCopyLoweringPass::rewriteSetCC(MachineBasicBlock &MBB,
if (!CondReg)
CondReg = promoteCondToReg(MBB, Pos, Loc, Cond);

if (X86::isSETZUCC(MI.getOpcode())) {
// SETZUCC is generated for register only for now.
assert(!MI.mayStore() && "Cannot handle memory variants");
assert(MI.getOperand(0).isReg() &&
"Cannot have a non-register defined operand to SETZUcc!");
Register OldReg = MI.getOperand(0).getReg();
// Drop Kill flags on the old register before replacing. CondReg may have
// a longer live range.
MRI->clearKillFlags(OldReg);
for (auto &Use : MRI->use_instructions(OldReg)) {
assert(Use.getOpcode() == X86::INSERT_SUBREG &&
"SETZUCC should be only used by INSERT_SUBREG");
Use.getOperand(2).setReg(CondReg);
// Recover MOV32r0 before INSERT_SUBREG, which removed by SETZUCC.
Register ZeroReg = MRI->createVirtualRegister(&X86::GR32RegClass);
BuildMI(*Use.getParent(), &Use, Use.getDebugLoc(), TII->get(X86::MOV32r0),
ZeroReg);
Use.getOperand(1).setReg(ZeroReg);
}
MI.eraseFromParent();
return;
}

// Rewriting a register def is trivial: we just replace the register and
// remove the setcc.
if (!MI.mayStore()) {
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/apx/setzucc.ll
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@KanRobert KanRobert Mar 4, 2025

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Sorry. I don't understand this. Why can't we just remove the testb %sil, %sil?

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@phoebewang phoebewang Mar 4, 2025

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The testb %sil, %sil is due to adcl $0, %ecx clobbers EFLAGS.

Original file line number Diff line number Diff line change
Expand Up @@ -60,11 +60,11 @@ define i32 @flags_copy_lowering() nounwind {
; CHECK-NEXT: setb %sil
; CHECK-NEXT: adcl $0, %ecx
; CHECK-NEXT: testb %sil, %sil
; CHECK-NEXT: setzune %dl
; CHECK-NEXT: testb %sil, %sil
; CHECK-NEXT: je .LBB4_3
; CHECK-NEXT: # %bb.2: # %bb1
; CHECK-NEXT: # in Loop: Header=BB4_1 Depth=1
; CHECK-NEXT: xorl %edx, %edx
; CHECK-NEXT: movb %sil, %dl
; CHECK-NEXT: testb %al, %al
; CHECK-NEXT: jne .LBB4_1
; CHECK-NEXT: .LBB4_3: # %bb2
Expand Down