Skip to content

[LLVM][SVE] Lower bfloat extends the same as other types. #129544

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Mar 4, 2025
Merged

[LLVM][SVE] Lower bfloat extends the same as other types. #129544

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
15 changes: 3 additions & 12 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -4503,18 +4503,9 @@ SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
if (VT.isScalableVector()) {
SDValue SrcVal = Op.getOperand(0);

if (SrcVal.getValueType().getScalarType() == MVT::bf16) {
// bf16 and f32 share the same exponent range so the conversion requires
// them to be aligned with the new mantissa bits zero'd. This is just a
// left shift that is best to isel directly.
if (VT == MVT::nxv2f32 || VT == MVT::nxv4f32)
return Op;

if (VT != MVT::nxv2f64)
return SDValue();

// Break other conversions in two with the first part converting to f32
// and the second using native f32->VT instructions.
if (VT == MVT::nxv2f64 && SrcVal.getValueType() == MVT::nxv2bf16) {
// Break conversion in two with the first part converting to f32 and the
// second using native f32->VT instructions.
SDLoc DL(Op);
return DAG.getNode(ISD::FP_EXTEND, DL, VT,
DAG.getNode(ISD::FP_EXTEND, DL, MVT::nxv2f32, SrcVal));
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -345,7 +345,7 @@ def AArch64fclamp : PatFrags<(ops node:$Zd, node:$Zn, node:$Zm),

def SDT_AArch64FCVT : SDTypeProfile<1, 3, [
SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisVec<3>,
SDTCVecEltisVT<1,i1>
SDTCVecEltisVT<1,i1>, SDTCisSameNumEltsAs<0,1>, SDTCisSameAs<0,3>
]>;

def SDT_AArch64FCVTR : SDTypeProfile<1, 4, [
Expand Down Expand Up @@ -2370,9 +2370,9 @@ let Predicates = [HasSVE_or_SME] in {
def : Pat<(nxv2f16 (AArch64fcvtr_mt (nxv2i1 (SVEAllActive:$Pg)), nxv2f32:$Zs, (i64 timm0_1), nxv2f16:$Zd)),
(FCVT_ZPmZ_StoH_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>;

def : Pat<(nxv4f32 (fpextend nxv4bf16:$op)),
def : Pat<(nxv4f32 (AArch64fcvte_mt (SVEAnyPredicate), nxv4bf16:$op, undef)),
(LSL_ZZI_S $op, (i32 16))>;
def : Pat<(nxv2f32 (fpextend nxv2bf16:$op)),
def : Pat<(nxv2f32 (AArch64fcvte_mt (SVEAnyPredicate), nxv2bf16:$op, undef)),
(LSL_ZZI_S $op, (i32 16))>;

// Signed integer -> Floating-point
Expand Down