[SPIR-V] Add SPV_INTEL_memory_access_aliasing extension #129800
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@llvm/pr-subscribers-llvm-ir @llvm/pr-subscribers-backend-spir-v Author: Dmitry Sidorov (MrSidims) ChangesSpec can be found here intel/llvm#15225
Patch is 38.52 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/129800.diff 22 Files Affected:
diff --git a/llvm/docs/SPIRVUsage.rst b/llvm/docs/SPIRVUsage.rst
index 93c53a04bc447..bed448ab7a383 100644
--- a/llvm/docs/SPIRVUsage.rst
+++ b/llvm/docs/SPIRVUsage.rst
@@ -173,6 +173,8 @@ list of supported SPIR-V extensions, sorted alphabetically by their extension na
- Adds decorations that can be applied to global (module scope) variables to help code generation for FPGA devices.
* - ``SPV_INTEL_media_block_io``
- Adds additional subgroup block read and write functionality that allow applications to flexibly specify the width and height of the block to read from or write to a 2D image.
+ * - ``SPV_INTEL_memory_access_aliasing``
+ - Adds instructions and decorations to specify memory access aliasing, similar to alias.scope and noalias LLVM metadata.
* - ``SPV_INTEL_optnone``
- Adds OptNoneINTEL value for Function Control mask that indicates a request to not optimize the function.
* - ``SPV_INTEL_split_barrier``
@@ -301,6 +303,10 @@ SPIR-V backend, along with their descriptions and argument details.
- None
- `[Type, Metadata]`
- Assigns decoration to values by associating them with metadatas. Not emitted directly but used to support SPIR-V representation in LLVM IR.
+ * - `int_spv_assign_aliasing_decoration`
+ - None
+ - `[Type, 32-bit Integer, Metadata]`
+ - Assigns one of two memory aliasing decorations (specified by the second argument) to instructions using original alasing list metadata node. Not emitted directly but used to support SPIR-V representation in LLVM IR.
* - `int_spv_track_constant`
- Type
- `[Type, Metadata]`
diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
index 38910ee263ee3..0c91d22fea1fa 100644
--- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td
+++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td
@@ -137,4 +137,7 @@ let TargetPrefix = "spv" in {
def int_spv_resource_store_typedbuffer
: DefaultAttrsIntrinsic<[], [llvm_any_ty, llvm_i32_ty, llvm_anyvector_ty]>;
+ // Memory aliasing intrinsics
+ def int_spv_assign_aliasing_decoration : Intrinsic<[], [llvm_any_ty, llvm_i32_ty, llvm_metadata_ty], [ImmArg<ArgIndex<1>>]>;
+
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp b/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
index 8b06a7197a11e..086145ee69fc0 100644
--- a/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVAsmPrinter.cpp
@@ -611,6 +611,9 @@ void SPIRVAsmPrinter::outputModuleSections() {
outputModuleSection(SPIRV::MB_DebugNames);
// 7c. Debug: all OpModuleProcessed instructions.
outputModuleSection(SPIRV::MB_DebugModuleProcessed);
+ // xxx. SPV_INTEL_memory_access_aliasing instructions go before 8.
+ // "All annotation instructions"
+ outputModuleSection(SPIRV::MB_AliasingInsts);
// 8. All annotation instructions (all decorations).
outputAnnotations(*M);
// 9. All type declarations (OpTypeXXX instructions), all constant
diff --git a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
index 78f6b188c45c1..d5d084da91901 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
@@ -683,6 +683,20 @@ bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
return false;
MIB.addUse(Arg.Regs[0]);
}
+
+ if (ST->canUseExtension(SPIRV::Extension::SPV_INTEL_memory_access_aliasing)) {
+ // Process aliasing metadata.
+ const CallBase *CI = Info.CB;
+ if (CI && CI->hasMetadata()) {
+ if (MDNode *MD = CI->getMetadata(LLVMContext::MD_alias_scope))
+ buildMemAliasingOpDecorate(ResVReg, MIRBuilder,
+ SPIRV::Decoration::AliasScopeINTEL, MD);
+ if (MDNode *MD = CI->getMetadata(LLVMContext::MD_noalias))
+ buildMemAliasingOpDecorate(ResVReg, MIRBuilder,
+ SPIRV::Decoration::NoAliasINTEL, MD);
+ }
+ }
+
return MIB.constrainAllUses(MIRBuilder.getTII(), *ST->getRegisterInfo(),
*ST->getRegBankInfo());
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
index 333e0131ac228..8d1714932c3c6 100644
--- a/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVCommandLine.cpp
@@ -53,6 +53,8 @@ static const std::map<std::string, SPIRV::Extension::Extension, std::less<>>
SPIRV::Extension::Extension::SPV_INTEL_subgroups},
{"SPV_INTEL_media_block_io",
SPIRV::Extension::Extension::SPV_INTEL_media_block_io},
+ {"SPV_INTEL_memory_access_aliasing",
+ SPIRV::Extension::Extension::SPV_INTEL_memory_access_aliasing},
{"SPV_INTEL_joint_matrix",
SPIRV::Extension::Extension::SPV_INTEL_joint_matrix},
{"SPV_KHR_uniform_group_instructions",
diff --git a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
index 5dfba8427258f..c83c6827ecd98 100644
--- a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
@@ -172,6 +172,7 @@ class SPIRVEmitIntrinsics
unsigned OperandToReplace,
IRBuilder<> &B);
void insertPtrCastOrAssignTypeInstr(Instruction *I, IRBuilder<> &B);
+ bool shouldTryToAddMemAliasingDecoration(Instruction *Inst);
void insertSpirvDecorations(Instruction *I, IRBuilder<> &B);
void processGlobalValue(GlobalVariable &GV, IRBuilder<> &B);
void processParamTypes(Function *F, IRBuilder<> &B);
@@ -1249,6 +1250,7 @@ void SPIRVEmitIntrinsics::replaceMemInstrUses(Instruction *Old,
llvm_unreachable("illegal aggregate intrinsic user");
}
}
+ New->copyMetadata(*Old);
Old->eraseFromParent();
}
@@ -1832,6 +1834,7 @@ Instruction *SPIRVEmitIntrinsics::visitStoreInst(StoreInst &I) {
Intrinsic::spv_store, {I.getValueOperand()->getType(), PtrOp->getType()},
{I.getValueOperand(), PtrOp, B.getInt16(Flags),
B.getInt8(I.getAlign().value())});
+ NewI->copyMetadata(I);
I.eraseFromParent();
return NewI;
}
@@ -2034,6 +2037,38 @@ void SPIRVEmitIntrinsics::insertAssignTypeIntrs(Instruction *I,
}
}
+bool SPIRVEmitIntrinsics::shouldTryToAddMemAliasingDecoration(
+ Instruction *Inst) {
+ const SPIRVSubtarget *STI = TM->getSubtargetImpl(*Inst->getFunction());
+ if (!STI->canUseExtension(
+ SPIRV::Extension::SPV_INTEL_memory_access_aliasing))
+ return false;
+ // Add aliasing decorations to internal load and store intrinsics
+ // and atomic instructions, skipping atomic store as it won't have ID to
+ // attach the decoration.
+ CallInst *CI = dyn_cast<CallInst>(Inst);
+ if (!CI)
+ return false;
+ if (Function *Fun = CI->getCalledFunction()) {
+ if (Fun->isIntrinsic()) {
+ switch (Fun->getIntrinsicID()) {
+ case Intrinsic::spv_load:
+ case Intrinsic::spv_store:
+ return true;
+ default:
+ return false;
+ }
+ }
+ std::string Name = getOclOrSpirvBuiltinDemangledName(Fun->getName());
+ const std::string Prefix = "__spirv_Atomic";
+ const bool IsAtomic = Name.find(Prefix) == 0;
+
+ if (!Fun->getReturnType()->isVoidTy() && IsAtomic)
+ return true;
+ }
+ return false;
+}
+
void SPIRVEmitIntrinsics::insertSpirvDecorations(Instruction *I,
IRBuilder<> &B) {
if (MDNode *MD = I->getMetadata("spirv.Decorations")) {
@@ -2041,6 +2076,27 @@ void SPIRVEmitIntrinsics::insertSpirvDecorations(Instruction *I,
B.CreateIntrinsic(Intrinsic::spv_assign_decoration, {I->getType()},
{I, MetadataAsValue::get(I->getContext(), MD)});
}
+ // Lower alias.scope/noalias metadata
+ {
+ auto processMemAliasingDecoration = [&](unsigned Kind) {
+ if (MDNode *AliasListMD = I->getMetadata(Kind)) {
+ if (shouldTryToAddMemAliasingDecoration(I)) {
+ uint32_t Dec = Kind == LLVMContext::MD_alias_scope
+ ? SPIRV::Decoration::AliasScopeINTEL
+ : SPIRV::Decoration::NoAliasINTEL;
+ SmallVector<Value *, 3> Args = {
+ I, ConstantInt::get(B.getInt32Ty(),
+ Dec),
+ MetadataAsValue::get(I->getContext(), AliasListMD)};
+ setInsertPointAfterDef(B, I);
+ B.CreateIntrinsic(Intrinsic::spv_assign_aliasing_decoration,
+ {I->getType()}, {Args});
+ }
+ }
+ };
+ processMemAliasingDecoration(LLVMContext::MD_alias_scope);
+ processMemAliasingDecoration(LLVMContext::MD_noalias);
+ }
}
void SPIRVEmitIntrinsics::processInstrAfterVisit(Instruction *I,
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
index 49b6b3bbb6cef..a22390b89f05f 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.cpp
@@ -96,6 +96,17 @@ bool SPIRVInstrInfo::isDecorationInstr(const MachineInstr &MI) const {
}
}
+bool SPIRVInstrInfo::isAliasingInstr(const MachineInstr &MI) const {
+ switch (MI.getOpcode()) {
+ case SPIRV::OpAliasDomainDeclINTEL:
+ case SPIRV::OpAliasScopeDeclINTEL:
+ case SPIRV::OpAliasScopeListDeclINTEL:
+ return true;
+ default:
+ return false;
+ }
+}
+
bool SPIRVInstrInfo::isHeaderInstr(const MachineInstr &MI) const {
switch (MI.getOpcode()) {
case SPIRV::OpCapability:
@@ -114,7 +125,8 @@ bool SPIRVInstrInfo::isHeaderInstr(const MachineInstr &MI) const {
case SPIRV::OpModuleProcessed:
return true;
default:
- return isTypeDeclInstr(MI) || isConstantInstr(MI) || isDecorationInstr(MI);
+ return isTypeDeclInstr(MI) || isConstantInstr(MI) ||
+ isDecorationInstr(MI) || isAliasingInstr(MI);
}
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
index 4e5059b4b8891..8fea120fcaf71 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.h
@@ -34,6 +34,7 @@ class SPIRVInstrInfo : public SPIRVGenInstrInfo {
bool isInlineAsmDefInstr(const MachineInstr &MI) const;
bool isTypeDeclInstr(const MachineInstr &MI) const;
bool isDecorationInstr(const MachineInstr &MI) const;
+ bool isAliasingInstr(const MachineInstr &MI) const;
bool canUseFastMathFlags(const MachineInstr &MI) const;
bool canUseNSW(const MachineInstr &MI) const;
bool canUseNUW(const MachineInstr &MI) const;
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
index 5e9a9bd145bca..a8f862271dbab 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
+++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td
@@ -948,3 +948,11 @@ def OpConvertHandleToSamplerINTEL: Op<6530, (outs ID:$res), (ins TYPE:$type, ID:
"$res = OpConvertHandleToSamplerINTEL $type $operand">;
def OpConvertHandleToSampledImageINTEL: Op<6531, (outs ID:$res), (ins TYPE:$type, ID:$operand),
"$res = OpConvertHandleToSampledImageINTEL $type $operand">;
+
+// SPV_INTEL_memory_access_aliasing
+def OpAliasDomainDeclINTEL: Op<5911, (outs ID:$res), (ins variable_ops),
+ "$res = OpAliasDomainDeclINTEL">;
+def OpAliasScopeDeclINTEL: Op<5912, (outs ID:$res), (ins ID:$AliasDomain, variable_ops),
+ "$res = OpAliasScopeDeclINTEL $AliasDomain">;
+def OpAliasScopeListDeclINTEL: Op<5913, (outs ID:$res), (ins variable_ops),
+ "$res = OpAliasScopeListDeclINTEL">;
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index e7d8fe5bd8015..f268fca9f50b0 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -1020,7 +1020,7 @@ bool SPIRVInstructionSelector::selectBitcast(Register ResVReg,
}
static void addMemoryOperands(MachineMemOperand *MemOp,
- MachineInstrBuilder &MIB) {
+ MachineInstrBuilder &MIB, MachineInstr &I) {
uint32_t SpvMemOp = static_cast<uint32_t>(SPIRV::MemoryOperand::None);
if (MemOp->isVolatile())
SpvMemOp |= static_cast<uint32_t>(SPIRV::MemoryOperand::Volatile);
@@ -1029,10 +1029,35 @@ static void addMemoryOperands(MachineMemOperand *MemOp,
if (MemOp->getAlign().value())
SpvMemOp |= static_cast<uint32_t>(SPIRV::MemoryOperand::Aligned);
+ [[maybe_unused]] MachineInstr *AliasList = nullptr;
+ [[maybe_unused]] MachineInstr *NoAliasList = nullptr;
+ MachineIRBuilder MIRBuilder(I);
+ const SPIRVSubtarget *ST =
+ static_cast<const SPIRVSubtarget *>(
+ &MIRBuilder.getMF().getSubtarget());
+ if (ST->canUseExtension(SPIRV::Extension::SPV_INTEL_memory_access_aliasing)) {
+ if (auto *MD = MemOp->getAAInfo().Scope) {
+ AliasList = getOrAddMemAliasingINTELInst(MIRBuilder, MD);
+ if (AliasList)
+ SpvMemOp |= static_cast<uint32_t>(
+ SPIRV::MemoryOperand::AliasScopeINTELMask);
+ }
+ if (auto *MD = MemOp->getAAInfo().NoAlias) {
+ NoAliasList = getOrAddMemAliasingINTELInst(MIRBuilder, MD);
+ if (NoAliasList)
+ SpvMemOp |= static_cast<uint32_t>(
+ SPIRV::MemoryOperand::NoAliasINTELMask);
+ }
+ }
+
if (SpvMemOp != static_cast<uint32_t>(SPIRV::MemoryOperand::None)) {
MIB.addImm(SpvMemOp);
if (SpvMemOp & static_cast<uint32_t>(SPIRV::MemoryOperand::Aligned))
MIB.addImm(MemOp->getAlign().value());
+ if (AliasList)
+ MIB.addUse(AliasList->getOperand(0).getReg());
+ if (NoAliasList)
+ MIB.addUse(NoAliasList->getOperand(0).getReg());
}
}
@@ -1081,7 +1106,7 @@ bool SPIRVInstructionSelector::selectLoad(Register ResVReg,
TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS);
addMemoryOperands(I.getOperand(2 + OpOffset).getImm(), MIB);
} else {
- addMemoryOperands(*I.memoperands_begin(), MIB);
+ addMemoryOperands(*I.memoperands_begin(), MIB, I);
}
return MIB.constrainAllUses(TII, TRI, RBI);
}
@@ -1123,7 +1148,7 @@ bool SPIRVInstructionSelector::selectStore(MachineInstr &I) const {
TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS);
addMemoryOperands(I.getOperand(2 + OpOffset).getImm(), MIB);
} else {
- addMemoryOperands(*I.memoperands_begin(), MIB);
+ addMemoryOperands(*I.memoperands_begin(), MIB, I);
}
return MIB.constrainAllUses(TII, TRI, RBI);
}
@@ -1201,7 +1226,7 @@ bool SPIRVInstructionSelector::selectMemOperation(Register ResVReg,
.addUse(SrcReg)
.addUse(I.getOperand(2).getReg());
if (I.getNumMemOperands())
- addMemoryOperands(*I.memoperands_begin(), MIB);
+ addMemoryOperands(*I.memoperands_begin(), MIB, I);
Result &= MIB.constrainAllUses(TII, TRI, RBI);
if (ResVReg.isValid() && ResVReg != MIB->getOperand(0).getReg())
Result &= BuildCOPY(ResVReg, MIB->getOperand(0).getReg(), I);
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
index fea3965dd8f2a..ea393a64351f7 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.cpp
@@ -567,6 +567,8 @@ void SPIRVModuleAnalysis::processOtherInstrs(const Module &M) {
collectOtherInstr(MI, MAI, SPIRV::MB_DebugNames, IS);
} else if (OpCode == SPIRV::OpEntryPoint) {
collectOtherInstr(MI, MAI, SPIRV::MB_EntryPoints, IS);
+ } else if (TII->isAliasingInstr(MI)) {
+ collectOtherInstr(MI, MAI, SPIRV::MB_AliasingInsts, IS);
} else if (TII->isDecorationInstr(MI)) {
collectOtherInstr(MI, MAI, SPIRV::MB_Annotations, IS);
collectFuncNames(MI, &*F);
@@ -1251,6 +1253,13 @@ void addInstrRequirements(const MachineInstr &MI,
}
break;
}
+ case SPIRV::OpAliasDomainDeclINTEL:
+ case SPIRV::OpAliasScopeDeclINTEL:
+ case SPIRV::OpAliasScopeListDeclINTEL: {
+ Reqs.addExtension(SPIRV::Extension::SPV_INTEL_memory_access_aliasing);
+ Reqs.addCapability(SPIRV::Capability::MemoryAccessAliasingINTEL);
+ break;
+ }
case SPIRV::OpBitReverse:
case SPIRV::OpBitFieldInsert:
case SPIRV::OpBitFieldSExtract:
diff --git a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h
index 2b3599259a739..0beb4af1c99f6 100644
--- a/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h
+++ b/llvm/lib/Target/SPIRV/SPIRVModuleAnalysis.h
@@ -35,6 +35,7 @@ enum ModuleSectionType {
MB_DebugNames, // All OpName and OpMemberName intrs.
MB_DebugStrings, // All OpString intrs.
MB_DebugModuleProcessed, // All OpModuleProcessed instructions.
+ MB_AliasingInsts, // SPV_INTEL_memory_access_aliasing instructions.
MB_Annotations, // OpDecorate, OpMemberDecorate etc.
MB_TypeConstVars, // OpTypeXXX, OpConstantXXX, and global OpVariables.
MB_NonSemanticGlobalDI, // OpExtInst with e.g. DebugSource, DebugTypeBasic.
diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
index 32f6af3d1440f..3da8e679cdeb1 100644
--- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp
@@ -813,11 +813,19 @@ static void insertSpirvDecorations(MachineFunction &MF, MachineIRBuilder MIB) {
SmallVector<MachineInstr *, 10> ToErase;
for (MachineBasicBlock &MBB : MF) {
for (MachineInstr &MI : MBB) {
- if (!isSpvIntrinsic(MI, Intrinsic::spv_assign_decoration))
+ if (!isSpvIntrinsic(MI, Intrinsic::spv_assign_decoration) &&
+ !isSpvIntrinsic(MI, Intrinsic::spv_assign_aliasing_decoration))
continue;
MIB.setInsertPt(*MI.getParent(), MI.getNextNode());
- buildOpSpirvDecorations(MI.getOperand(1).getReg(), MIB,
- MI.getOperand(2).getMetadata());
+ if (isSpvIntrinsic(MI, Intrinsic::spv_assign_decoration)) {
+ buildOpSpirvDecorations(MI.getOperand(1).getReg(), MIB,
+ MI.getOperand(2).getMetadata());
+ } else {
+ buildMemAliasingOpDecorate(MI.getOperand(1).getReg(), MIB,
+ MI.getOperand(2).getImm(),
+ MI.getOperand(3).getMetadata());
+ }
+
ToErase.push_back(&MI);
}
}
diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
index c7cb0a50752fe..a871518e2094c 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
+++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td
@@ -311,6 +311,7 @@ defm SPV_INTEL_joint_matrix : ExtensionOperand<114>;
defm SPV_INTEL_float_controls2 : ExtensionOperand<115>;
defm SPV_INTEL_bindless_images : ExtensionOperand<116>;
defm SPV_INTEL_long_composites : ExtensionOperand<117>;
+defm SPV_INTEL_memory_access_aliasing : ExtensionOperand<118>;
//===----------------------------------------------------------------------===//
// Multiclass used to define Capabilities enum values and at the same time
@@ -509,6 +510,7 @@ defm FloatingPointModeINTEL : CapabilityOperand<5583, 0, 0, [SPV_INTEL_float_con
defm FunctionFloatControlINTEL : CapabilityOperand<5821, 0, 0, [SPV_INTEL_float_controls2], []>;
defm LongCompositesINTEL : CapabilityOperand<6089, 0, 0, [SPV_INTEL_long_composites], []>;
defm BindlessImagesINTEL : CapabilityOperand<6528, 0, 0, [SPV_INTEL_bindless_images], []>;
+defm MemoryAccessAliasingINTEL : CapabilityOperand<5910, 0, 0, [SPV_INTEL_memory_access_aliasing], []>;
//===----------------------------------------------------------------------===//
// Multiclass used to define SourceLanguage enum values and at the same time
@@ -1257,6 +1259,8 @@ defm ImplementInRegisterMapINTEL : DecorationOperand<6191, 0, 0, [], [GlobalVari
defm FunctionRoundingModeINTEL : DecorationOperand<5822, 0, 0, [], [FunctionFloatControlINTEL]>;
defm FunctionDenormModeINTEL : DecorationOperand<5823, 0, 0, [], [FunctionFloatControlINTEL]>;
defm FunctionFloatingPointModeINTEL : DecorationOperand<6080, 0, 0, [], [FunctionFloatControlINTEL]>;
+defm AliasScopeINTEL : DecorationOperand<5914, 0, 0, [], [MemoryAccessAliasingINTEL]>;
+defm NoAliasINTEL : DecorationOperand<5915, 0, 0, [], [MemoryAccessAliasingINTEL]>;
//===----------------------------------------------------------------------===//
// Multiclass used to define BuiltIn...
[truncated]
|
MrSidims
commented
Mar 4, 2025
Contributor
Author
|
@vmaksimo please also take a look |
|
✅ With the latest revision this PR passed the C/C++ code formatter. |
Spec can be found here intel/llvm#15225 TODO for future patches: - During spec review need to decide whether only FunctionCall or Atomic instructions can be decorated and if not - move the code around adding handling for other instructions; - Handle optional string metadata; - Handle LLVM atomic instructions; - Handle SPIR-V friendly atomic calls returning via sret argument. Signed-off-by: Sidorov, Dmitry <[email protected]>
MrSidims
commented
Mar 4, 2025
| const std::string Prefix = "__spirv_Atomic"; | ||
| const bool IsAtomic = Name.find(Prefix) == 0; | ||
|
|
||
| if (!Fun->getReturnType()->isVoidTy() && IsAtomic) |
Contributor
Author
There was a problem hiding this comment.
note: I have considered moving it to lowerBuiltin, but here (imho) it looks nicer. If/when in the future we allow more instructions to be decorated - then it can be done.
Signed-off-by: Sidorov, Dmitry <[email protected]>
llvm/test/CodeGen/SPIRV/extensions/SPV_INTEL_memory_access_aliasing/alias-barrier.ll
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Signed-off-by: Sidorov, Dmitry <[email protected]>
Signed-off-by: Sidorov, Dmitry <[email protected]>
VyacheslavLevytskyy
approved these changes
Mar 6, 2025
Signed-off-by: Sidorov, Dmitry <[email protected]>
VishMCW
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Mar 18, 2025
Spec can be found here intel/llvm#15225 TODO for future patches: - During spec review need to decide whether only FunctionCall or Atomic instructions can be decorated and if not - move the code around adding handling for other instructions; - Handle optional string metadata; - Handle LLVM atomic instructions; - Handle SPIR-V friendly atomic calls returning via sret argument. Signed-off-by: Sidorov, Dmitry <[email protected]>
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Spec can be found here intel/llvm#15225
TODO for future patches: