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[RISCV] Collect shuffle mask for the lane not by createSequentialMask #129830

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Merged
tclin914 merged 2 commits into from
Mar 5, 2025
Merged

[RISCV] Collect shuffle mask for the lane not by createSequentialMask #129830

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cd71fa5
[RISCV] Collect shuffle mask for the lane not by createSequentialMask
tclin914 Mar 4, 2025
a16222b
clang-format the change
tclin914 Mar 5, 2025
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10 changes: 8 additions & 2 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -23056,12 +23056,18 @@ bool RISCVTargetLowering::lowerInterleavedStore(StoreInst *SI,
{VTy, SI->getPointerOperandType(), XLenTy});

SmallVector<Value *, 10> Ops;
SmallVector<int, 16> NewShuffleMask;

for (unsigned i = 0; i < Factor; i++) {
// Collect shuffle mask for this lane.
for (unsigned j = 0; j < VTy->getNumElements(); j++)
NewShuffleMask.push_back(Mask[i + Factor * j]);

Value *Shuffle = Builder.CreateShuffleVector(
SVI->getOperand(0), SVI->getOperand(1),
createSequentialMask(Mask[i], VTy->getNumElements(), 0));
SVI->getOperand(0), SVI->getOperand(1), NewShuffleMask);
Ops.push_back(Shuffle);

NewShuffleMask.clear();
}
// This VL should be OK (should be executable in one vsseg instruction,
// potentially under larger LMULs) because we checked that the fixed vector
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8 changes: 2 additions & 6 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1394,16 +1394,12 @@ define void @store_factor4_one_active_fullwidth(ptr %ptr, <16 x i32> %v) {
ret void
}

; TODO: This could be a vslidedown followed by a strided store
define void @store_factor4_one_active_slidedown(ptr %ptr, <4 x i32> %v) {
; CHECK-LABEL: store_factor4_one_active_slidedown:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v9, v8, 1
; CHECK-NEXT: vslideup.vi v10, v8, 1
; CHECK-NEXT: vmv.v.v v11, v10
; CHECK-NEXT: vmv.v.v v12, v10
; CHECK-NEXT: vsseg4e32.v v9, (a0)
; CHECK-NEXT: vslidedown.vi v8, v8, 1
; CHECK-NEXT: vsseg4e32.v v8, (a0)
; CHECK-NEXT: ret
%v0 = shufflevector <4 x i32> %v, <4 x i32> poison, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 2, i32 undef, i32 undef, i32 undef, i32 3, i32 undef, i32 undef, i32 undef, i32 4, i32 undef, i32 undef, i32 undef>
store <16 x i32> %v0, ptr %ptr
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