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[X86] Extend shuf128(concat(x,y),concat(z,w)) -> shuf128(widen(y),widen(w)) folds to peek through bitcasts #129896

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merged 2 commits into from
Mar 6, 2025
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[X86] Extend shuf128(concat(x,y),concat(z,w)) -> shuf128(widen(y),widen(w)) folds to peek through bitcasts #129896

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982a8e7
[X86] Extend shuf128(concat(x,y),concat(z,w)) -> shuf128(widen(y),wid…
RKSimon Mar 5, 2025
e546e6f
Move if clause ordering back to cheapest first.
RKSimon Mar 5, 2025
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13 changes: 7 additions & 6 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -42365,10 +42365,10 @@ static SDValue combineTargetShuffle(SDValue N, const SDLoc &DL,
// If we're permuting the upper 256-bits subvectors of a concatenation, then
// see if we can peek through and access the subvector directly.
if (VT.is512BitVector()) {
// 512-bit mask uses 4 x i2 indices - if the msb is always set then only the
// upper subvector is used.
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
// 512-bit mask uses 4 x i2 indices - if the msb is always set then only
// the upper subvector is used.
SDValue LHS = peekThroughBitcasts(N->getOperand(0));
SDValue RHS = peekThroughBitcasts(N->getOperand(1));
uint64_t Mask = N->getConstantOperandVal(2);
SmallVector<SDValue> LHSOps, RHSOps;
SDValue NewLHS, NewRHS;
Expand All @@ -42383,8 +42383,9 @@ static SDValue combineTargetShuffle(SDValue N, const SDLoc &DL,
Mask &= ~0xA0;
}
if (NewLHS || NewRHS)
return DAG.getNode(X86ISD::SHUF128, DL, VT, NewLHS ? NewLHS : LHS,
NewRHS ? NewRHS : RHS,
return DAG.getNode(X86ISD::SHUF128, DL, VT,
DAG.getBitcast(VT, NewLHS ? NewLHS : LHS),
DAG.getBitcast(VT, NewRHS ? NewRHS : RHS),
DAG.getTargetConstant(Mask, DL, MVT::i8));
}
return SDValue();
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