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[X86][APX] Support peephole optimization with CCMP instruction #129994

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Merged
merged 5 commits into from
Mar 12, 2025
Merged

[X86][APX] Support peephole optimization with CCMP instruction #129994

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dcc1099
[X86] Support peephole optimization with CCMP instruction
fzou1 Dec 19, 2024
3511b19
Add checks and LIT tests
fzou1 Mar 10, 2025
ce9e3ab
Add check to ensure CCMP opcode is same
fzou1 Mar 10, 2025
df7cb15
Add two sub-tests in ccmp LIT test for validate peephole optimization.
fzou1 Mar 10, 2025
1d44f40
Update comments in test.
fzou1 Mar 11, 2025
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4 changes: 2 additions & 2 deletions llvm/lib/Target/X86/X86InstrConditionalCompare.td
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Original file line number Diff line number Diff line change
Expand Up @@ -36,7 +36,7 @@ class Ctest<bits<8> o, Format f, X86TypeInfo t, DAGOperand op1, DAGOperand op2>:
//===----------------------------------------------------------------------===//
// CCMP Instructions
//
let SchedRW = [WriteALU] in {
let SchedRW = [WriteALU], isCompare = 1 in {
def CCMP8rr : Ccmp<0x38, MRMDestReg, Xi8, GR8, GR8>;
def CCMP16rr: Ccmp<0x39, MRMDestReg, Xi16, GR16, GR16>, PD;
def CCMP32rr: Ccmp<0x39, MRMDestReg, Xi32, GR32, GR32>;
Expand All @@ -55,7 +55,7 @@ let SchedRW = [WriteALU] in {
def CCMP64ri32: Ccmp<0x81, MRM7r, Xi64, GR64, i64i32imm>;
}

let mayLoad = 1 in {
let mayLoad = 1, isCompare = 1 in {
let SchedRW = [WriteALU.Folded] in {
def CCMP16mi8: Ccmp<0x83, MRM7m, Xi16, i16mem, i16i8imm>, PD;
def CCMP32mi8: Ccmp<0x83, MRM7m, Xi32, i32mem, i32i8imm>;
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18 changes: 18 additions & 0 deletions llvm/lib/Target/X86/X86InstrInfo.cpp
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Expand Up @@ -4854,6 +4854,10 @@ bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
case X86::CMP32ri:
case X86::CMP16ri:
case X86::CMP8ri:
case X86::CCMP64ri32:
case X86::CCMP32ri:
case X86::CCMP16ri:
case X86::CCMP8ri:
SrcReg = MI.getOperand(0).getReg();
SrcReg2 = 0;
if (MI.getOperand(1).isImm()) {
Expand Down Expand Up @@ -4951,6 +4955,20 @@ bool X86InstrInfo::isRedundantFlagInstr(const MachineInstr &FlagI,
}
return false;
}
case X86::CCMP64ri32:
case X86::CCMP32ri:
case X86::CCMP16ri:
case X86::CCMP8ri: {
// The CCMP instruction should not be optimized if the scc/dfv in it is not
// same as the one in previous CCMP instruction.
unsigned Opcode = FlagI.getOpcode();
if (Opcode == X86::CCMP64ri32 || Opcode == X86::CCMP32ri ||
Opcode == X86::CCMP16ri || Opcode == X86::CCMP8ri)
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@phoebewang phoebewang Mar 10, 2025

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Do we need FlagI.getOpcode() == OI.getOpcode()?

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@fzou1 fzou1 Mar 10, 2025

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Yes. Updated. It can prevent incorrect optimization (see CCMP + CMP combination in opt_redundant_flags_adjusted_imm_noopt_5 MIR sub-test). Thanks.

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@phoebewang phoebewang Mar 11, 2025

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This doesn't prevent CCMP + CMP, just e.g., CCMP64ri32 + CCMP16ri. I don't know if we have this pattern in real workload.

if (OI.getOperand(2).getImm() != FlagI.getOperand(2).getImm() ||
(OI.getOperand(3).getImm() != FlagI.getOperand(3).getImm()))
return false;
[[fallthrough]];
}
case X86::CMP64ri32:
case X86::CMP32ri:
case X86::CMP16ri:
Expand Down
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