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[AMDGPU] Add GFX12 S_ALLOC_VGPR instruction #130018

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Merged
rovka merged 2 commits into from
Mar 10, 2025
Merged

[AMDGPU] Add GFX12 S_ALLOC_VGPR instruction #130018

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3cacd07
[AMDGPU] Add GFX12 S_ALLOC_VGPR instruction
jasilvanus Mar 30, 2023
049c04b
More tests
rovka Mar 7, 2025
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7 changes: 7 additions & 0 deletions llvm/lib/Target/AMDGPU/SOPInstructions.td
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Original file line number Diff line number Diff line change
Expand Up @@ -423,6 +423,12 @@ let SubtargetPredicate = isGFX11Plus in {
}
} // End SubtargetPredicate = isGFX11Plus

let SubtargetPredicate = isGFX12Plus in {
let hasSideEffects = 1, Defs = [SCC] in {
def S_ALLOC_VGPR : SOP1_0_32 <"s_alloc_vgpr">;
}
} // End SubtargetPredicate = isGFX12Plus

class SOP1_F32_Inst<string opName, SDPatternOperator Op, ValueType vt0=f32,
ValueType vt1=vt0> :
SOP1_32<opName, [(set vt0:$sdst, (UniformUnaryFrag<Op> vt1:$src0))]>;
Expand Down Expand Up @@ -2048,6 +2054,7 @@ defm S_GET_BARRIER_STATE_M0 : SOP1_M0_Real_gfx12<0x050>;
defm S_BARRIER_SIGNAL_IMM : SOP1_IMM_Real_gfx12<0x04e>;
defm S_BARRIER_SIGNAL_ISFIRST_IMM : SOP1_IMM_Real_gfx12<0x04f>;
defm S_GET_BARRIER_STATE_IMM : SOP1_IMM_Real_gfx12<0x050>;
defm S_ALLOC_VGPR : SOP1_Real_gfx12<0x053>;
defm S_SLEEP_VAR : SOP1_IMM_Real_gfx12<0x058>;

//===----------------------------------------------------------------------===//
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3 changes: 3 additions & 0 deletions llvm/test/MC/AMDGPU/gfx11_unsupported.s
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Expand Up @@ -322,6 +322,9 @@ image_sample_cd_o v252, v[1:4], s[8:15], s[12:15] dmask:0x1
image_sample_cd_o_g16 v[5:6], v[1:4], s[8:15], s[12:15] dmask:0x3
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU

s_alloc_vgpr s0
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU

s_atomic_add flat_scratch_hi, s[2:3], s0
// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU

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15 changes: 15 additions & 0 deletions llvm/test/MC/AMDGPU/gfx12_asm_sop1.s
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@@ -1,5 +1,20 @@
// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1200 %s | FileCheck --check-prefix=GFX12 %s

s_alloc_vgpr 0x1235
// GFX12: encoding: [0xff,0x53,0x80,0xbe,0x35,0x12,0x00,0x00]

s_alloc_vgpr 18
// GFX12: encoding: [0x92,0x53,0x80,0xbe]

s_alloc_vgpr s35
// GFX12: encoding: [0x23,0x53,0x80,0xbe]

s_alloc_vgpr m0
// GFX12: encoding: [0x7d,0x53,0x80,0xbe]

s_alloc_vgpr scc
// GFX12: encoding: [0xfd,0x53,0x80,0xbe]

s_sleep_var 0x1234
// GFX12: encoding: [0xff,0x58,0x80,0xbe,0x34,0x12,0x00,0x00]

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9 changes: 9 additions & 0 deletions llvm/test/MC/AMDGPU/gfx12_err.s
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Expand Up @@ -116,3 +116,12 @@ s_prefetch_inst s[14:15], 0xffffff, m0, 7

s_endpgm_ordered_ps_done
// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU

s_alloc_vgpr v0
// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

s_alloc_vgpr exec
// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction

s_alloc_vgpr vcc
// GFX12-ERR: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
9 changes: 9 additions & 0 deletions llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_sop1.txt
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@@ -1,5 +1,14 @@
# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX12 %s

# GFX12: s_alloc_vgpr 0x1235 ; encoding: [0xff,0x53,0x80,0xbe,0x35,0x12,0x00,0x00]
0xff,0x53,0x80,0xbe,0x35,0x12,0x00,0x00

# GFX12: s_alloc_vgpr 18 ; encoding: [0x92,0x53,0x80,0xbe]
0x92,0x53,0x80,0xbe

# GFX12: s_alloc_vgpr s35 ; encoding: [0x23,0x53,0x80,0xbe]
0x23,0x53,0x80,0xbe

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@arsenm arsenm Mar 7, 2025

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Does this need error tests for VGPRs, or the exotic scalar registers?

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@rovka rovka Mar 7, 2025

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Done. I'm not sure which ones are the exotic SGPRs, I added tests for m0, scc, vcc and exec. We don't accept the last 2 (although I think sp3 accepts all of them).

# GFX12: s_sleep_var 0x1234 ; encoding: [0xff,0x58,0x80,0xbe,0x34,0x12,0x00,0x00]
0xff,0x58,0x80,0xbe,0x34,0x12,0x00,0x00

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