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[HLSL] Make sure isSigned flag is set on target type for TypedBuffer resources with signed int vectors #130223

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Merged
merged 1 commit into from
Mar 14, 2025
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[HLSL] Make sure isSigned flag is set on target type for TypedBuffer resources with signed int vectors #130223

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10 changes: 8 additions & 2 deletions clang/lib/CodeGen/Targets/DirectX.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -59,8 +59,14 @@ llvm::Type *DirectXTargetCodeGenInfo::getHLSLType(
SmallVector<unsigned, 3> Ints = {/*IsWriteable*/ ResAttrs.ResourceClass ==
llvm::dxil::ResourceClass::UAV,
/*IsROV*/ ResAttrs.IsROV};
if (!ResAttrs.RawBuffer)
Ints.push_back(/*IsSigned*/ ContainedTy->isSignedIntegerType());
if (!ResAttrs.RawBuffer) {
const clang::Type *ElemType = ContainedTy->getUnqualifiedDesugaredType();
if (ElemType->isVectorType())
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@bob80905 bob80905 Mar 14, 2025

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Does it make sense to add a while loop here?
Could it be more than a 2D vector?

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@hekota hekota Mar 14, 2025

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No, vectors cannot be nested, only arrays.

ElemType = cast<clang::VectorType>(ElemType)
->getElementType()
->getUnqualifiedDesugaredType();
Ints.push_back(/*IsSigned*/ ElemType->isSignedIntegerType());
}

return llvm::TargetExtType::get(Ctx, TypeName, {ElemType}, Ints);
}
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7 changes: 4 additions & 3 deletions clang/test/CodeGenHLSL/builtins/RWBuffer-elementtype.hlsl
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Original file line number Diff line number Diff line change
Expand Up @@ -10,10 +10,11 @@
// DXIL: %"class.hlsl::RWBuffer.5" = type { target("dx.TypedBuffer", half, 1, 0, 0) }
// DXIL: %"class.hlsl::RWBuffer.6" = type { target("dx.TypedBuffer", float, 1, 0, 0) }
// DXIL: %"class.hlsl::RWBuffer.7" = type { target("dx.TypedBuffer", double, 1, 0, 0) }
// DXIL: %"class.hlsl::RWBuffer.8" = type { target("dx.TypedBuffer", <4 x i16>, 1, 0, 0) }
// DXIL: %"class.hlsl::RWBuffer.8" = type { target("dx.TypedBuffer", <4 x i16>, 1, 0, 1) }
// DXIL: %"class.hlsl::RWBuffer.9" = type { target("dx.TypedBuffer", <3 x i32>, 1, 0, 0) }
// DXIL: %"class.hlsl::RWBuffer.10" = type { target("dx.TypedBuffer", <2 x half>, 1, 0, 0) }
// DXIL: %"class.hlsl::RWBuffer.11" = type { target("dx.TypedBuffer", <3 x float>, 1, 0, 0) }
// DXIL: %"class.hlsl::RWBuffer.12" = type { target("dx.TypedBuffer", <4 x i32>, 1, 0, 1) }

// SPIRV: %"class.hlsl::RWBuffer" = type { target("spirv.Image", i16, 5, 2, 0, 0, 2, 0) }
// SPIRV: %"class.hlsl::RWBuffer.0" = type { target("spirv.Image", i16, 5, 2, 0, 0, 2, 0) }
Expand All @@ -28,8 +29,7 @@
// SPIRV: %"class.hlsl::RWBuffer.9" = type { target("spirv.Image", i32, 5, 2, 0, 0, 2, 0) }
// SPIRV: %"class.hlsl::RWBuffer.10" = type { target("spirv.Image", half, 5, 2, 0, 0, 2, 0) }
// SPIRV: %"class.hlsl::RWBuffer.11" = type { target("spirv.Image", float, 5, 2, 0, 0, 2, 0) }


// SPIRV: %"class.hlsl::RWBuffer.12" = type { target("spirv.Image", i32, 5, 2, 0, 0, 2, 0) }

RWBuffer<int16_t> BufI16;
RWBuffer<uint16_t> BufU16;
Expand All @@ -44,6 +44,7 @@ RWBuffer< vector<int16_t, 4> > BufI16x4;
RWBuffer< vector<uint, 3> > BufU32x3;
RWBuffer<half2> BufF16x2;
RWBuffer<float3> BufF32x3;
RWBuffer<int4> BufI32x4;
// TODO: RWBuffer<snorm half> BufSNormF16; -> 11
// TODO: RWBuffer<unorm half> BufUNormF16; -> 12
// TODO: RWBuffer<snorm float> BufSNormF32; -> 13
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