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[RISCV] Fix incorrect mask of shuffle vector in the test. (NFC) #130244

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Merged
merged 1 commit into from
Mar 10, 2025
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[RISCV] Fix incorrect mask of shuffle vector in the test. (NFC) #130244

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20 changes: 4 additions & 16 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -380,30 +380,18 @@ entry:
ret void
}

; TODO: Allow an undef initial element
define void @vnsrl_0_i8_undef3(ptr %in, ptr %out) {
; CHECK-LABEL: vnsrl_0_i8_undef3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 16, e8, mf2, ta, ma
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmv.v.i v0, 8
; CHECK-NEXT: vsetivli zero, 8, e8, mf4, ta, mu
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: li a0, -32
; CHECK-NEXT: vadd.vv v9, v9, v9
; CHECK-NEXT: vadd.vi v9, v9, -8
; CHECK-NEXT: vslidedown.vi v10, v8, 2
; CHECK-NEXT: vslidedown.vi v10, v8, 3, v0.t
; CHECK-NEXT: vmv.s.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 8
; CHECK-NEXT: vsetivli zero, 8, e8, mf4, ta, mu
; CHECK-NEXT: vrgather.vv v10, v8, v9, v0.t
; CHECK-NEXT: vse8.v v10, (a1)
; CHECK-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vse8.v v8, (a1)
; CHECK-NEXT: ret
entry:
%0 = load <16 x i8>, ptr %in, align 1
%shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 undef, i32 undef, i32 4, i32 6, i32 6, i32 10, i32 12, i32 14>
%shuffle.i5 = shufflevector <16 x i8> %0, <16 x i8> poison, <8 x i32> <i32 undef, i32 undef, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
store <8 x i8> %shuffle.i5, ptr %out, align 1
ret void
}
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