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[AMDGPU] frame index elimination hit assertion for scavenged nonreg #130287

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Merged
PankajDwivedi-25 merged 8 commits into from
Mar 17, 2025
Merged

[AMDGPU] frame index elimination hit assertion for scavenged nonreg #130287

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f596226
[WIP][AMDGPU] frame index elimination hit assertion for scavenged nonreg
PankajDwivedi-25 Mar 7, 2025
a628294
fall back to default handling if scavenger couldn't find valid reg
PankajDwivedi-25 Mar 7, 2025
bd60c1f
address review
PankajDwivedi-25 Mar 7, 2025
fb7cb89
added mir test
PankajDwivedi-25 Mar 10, 2025
9eac68f
Update failing test
PankajDwivedi-25 Mar 12, 2025
c69df65
merge failing test to common file
PankajDwivedi-25 Mar 13, 2025
6141f53
fix: fold the offset into FIOp if scavenger couldn't find free sgpr
PankajDwivedi-25 Mar 13, 2025
0866a23
address reviews
PankajDwivedi-25 Mar 13, 2025
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37 changes: 21 additions & 16 deletions llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2769,12 +2769,15 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
// available.
if (!TmpReg)
TmpReg = RS->scavengeRegisterBackwards(AMDGPU::SReg_32_XM0RegClass,
MI, false, 0);
BuildMI(*MBB, *MI, DL, TII->get(AMDGPU::S_LSHR_B32))
.addDef(TmpReg, RegState::Renamable)
.addReg(FrameReg)
.addImm(ST.getWavefrontSizeLog2())
.setOperandDead(3); // Set SCC dead
MI, /*RestoreAfter=*/false, 0,
/*AllowSpill=*/false);
if (TmpReg) {
BuildMI(*MBB, *MI, DL, TII->get(AMDGPU::S_LSHR_B32))
.addDef(TmpReg, RegState::Renamable)
.addReg(FrameReg)
.addImm(ST.getWavefrontSizeLog2())
.setOperandDead(3); // Set SCC dead
}
MaterializedReg = TmpReg;
}

Expand Down Expand Up @@ -2802,18 +2805,20 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
DstReg = TmpReg;
}

auto AddI32 = BuildMI(*MBB, *MI, DL, MI->getDesc())
.addDef(DstReg, RegState::Renamable)
.addReg(MaterializedReg, RegState::Kill)
.add(OtherOp);
if (DeadSCC)
AddI32.setOperandDead(3);
if (TmpReg) {
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@arsenm arsenm Mar 14, 2025

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The condition here still doesn't make sense. The TmpReg is not used below. I'm confused by the whole flow now, it would make more sense to check MaterializedReg

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@PankajDwivedi-25 PankajDwivedi-25 Mar 17, 2025

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well, here we have reached at the point, where we update the original DstReg with TmpReg.
so now if tmp is valid it will work perfectly. In the case if it is not we have to make condition on DstReg or TmpReg.
Materializedreg is FrameReg at this point making check on that, I don't think make sense?

obviously TmpReg is not getting used directly but we update here DstReg with TmpReg.

auto AddI32 = BuildMI(*MBB, *MI, DL, MI->getDesc())
.addDef(DstReg, RegState::Renamable)
.addReg(MaterializedReg, RegState::Kill)
.add(OtherOp);
if (DeadSCC)
AddI32.setOperandDead(3);

MaterializedReg = DstReg;
MaterializedReg = DstReg;

OtherOp.ChangeToRegister(MaterializedReg, false);
OtherOp.setIsKill(true);
OtherOp.setIsRenamable(true);
OtherOp.ChangeToRegister(MaterializedReg, false);
OtherOp.setIsKill(true);
OtherOp.setIsRenamable(true);
}
FIOp->ChangeToImmediate(Offset);
} else {
// If we don't have any other offset to apply, we can just directly
Expand Down
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