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[RISCV] Add combine for shadd family of instructions. #130829

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Merged
merged 10 commits into from
Mar 31, 2025
Merged

[RISCV] Add combine for shadd family of instructions. #130829

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df5bcbf
[RISCV] Add combine for shadd family of instructions.
stefanp-synopsys Mar 11, 2025
38cfa79
Simplified the code as per comments.
stefanp-synopsys Mar 12, 2025
b60ccb8
Fixed a number of nits and added SDPatternMatch
stefanp-synopsys Mar 13, 2025
d452f5d
Fix clang-format.
stefanp-synopsys Mar 13, 2025
107d3d0
Figured out why the test case started failing and fixed it.
stefanp-synopsys Mar 14, 2025
30e5845
Fixed the issues with SDPatternMatch use.
stefanp-synopsys Mar 17, 2025
373f2a8
Fix formatting.
stefanp-synopsys Mar 17, 2025
c76c64e
Added an assert and removed the commutative from the shift.
stefanp-synopsys Mar 17, 2025
a335458
Renamed the helper function to combineShlAddIAddImpl and added all of…
stefanp-synopsys Mar 18, 2025
c54ae87
Added more testcases and fixed the signed / unsigned issue.
stefanp-synopsys Mar 18, 2025
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5 changes: 3 additions & 2 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -14325,10 +14325,11 @@ static bool checkAddiForShift(SDValue AddI, int64_t &AddConst,

APInt AddVal;
SDValue SHLVal;
sd_match(AddI, m_Add(m_Value(SHLVal), m_ConstInt(AddVal)));
assert(sd_match(AddI, m_Add(m_Value(SHLVal), m_ConstInt(AddVal))) &&
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@mshockwave mshockwave Mar 17, 2025

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This entire sd_match statement will not be executed if LLVM is not built with assertion enabled (e.g. normal Release build). I would recommend something like this:

bool IsAddI = sd_match(AddI, ...);
assert(IsAddI && "...");
(void)IsAddI;

"Expected an addi with a constant addition.");

APInt VShift;
if (!sd_match(SHLVal, m_c_BinOp(ISD::SHL, m_Value(), m_ConstInt(VShift))))
if (!sd_match(SHLVal, m_BinOp(ISD::SHL, m_Value(), m_ConstInt(VShift))))
return false;

if (VShift.slt(1) || VShift.sgt(3))
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