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[RISCV] Remove some unnecessary hasSideEffects = 0 and sink some to their base class. NFC #131044

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Merged
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Mar 13, 2025
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[RISCV] Remove some unnecessary hasSideEffects = 0 and sink some to their base class. NFC #131044

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34 changes: 11 additions & 23 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1238,6 +1238,7 @@ class VPseudoBinaryNoMaskRoundingMode<VReg RetClass,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = !interleave([Constraint, "$rd = $passthru"], ",");
let TargetOverlapConstraintType = TargetConstraintType;
let HasVLOp = 1;
Expand All @@ -1262,6 +1263,7 @@ class VPseudoBinaryMaskPolicyRoundingMode<VReg RetClass,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = !interleave([Constraint, "$rd = $passthru"], ",");
let TargetOverlapConstraintType = TargetConstraintType;
let HasVLOp = 1;
Expand Down Expand Up @@ -6405,7 +6407,7 @@ defm PseudoVFRSUB : VPseudoVALU_VF_RM;
//===----------------------------------------------------------------------===//
// 13.3. Vector Widening Floating-Point Add/Subtract Instructions
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true, hasSideEffects = 0 in {
let mayRaiseFPException = true in {
defm PseudoVFWADD : VPseudoVFWALU_VV_VF_RM;
defm PseudoVFWSUB : VPseudoVFWALU_VV_VF_RM;
defm PseudoVFWADD : VPseudoVFWALU_WV_WF_RM;
Expand All @@ -6415,7 +6417,7 @@ defm PseudoVFWSUB : VPseudoVFWALU_WV_WF_RM;
//===----------------------------------------------------------------------===//
// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true, hasSideEffects = 0 in {
let mayRaiseFPException = true in {
defm PseudoVFMUL : VPseudoVFMUL_VV_VF_RM;
defm PseudoVFDIV : VPseudoVFDIV_VV_VF_RM;
defm PseudoVFRDIV : VPseudoVFRDIV_VF_RM;
Expand All @@ -6424,14 +6426,14 @@ defm PseudoVFRDIV : VPseudoVFRDIV_VF_RM;
//===----------------------------------------------------------------------===//
// 13.5. Vector Widening Floating-Point Multiply
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true, hasSideEffects = 0 in {
let mayRaiseFPException = true in {
defm PseudoVFWMUL : VPseudoVWMUL_VV_VF_RM;
}

//===----------------------------------------------------------------------===//
// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true, hasSideEffects = 0 in {
let mayRaiseFPException = true in {
defm PseudoVFMACC : VPseudoVMAC_VV_VF_AAXA_RM;
defm PseudoVFNMACC : VPseudoVMAC_VV_VF_AAXA_RM;
defm PseudoVFMSAC : VPseudoVMAC_VV_VF_AAXA_RM;
Expand All @@ -6445,7 +6447,7 @@ defm PseudoVFNMSUB : VPseudoVMAC_VV_VF_AAXA_RM;
//===----------------------------------------------------------------------===//
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true, hasSideEffects = 0 in {
let mayRaiseFPException = true in {
defm PseudoVFWMACC : VPseudoVWMAC_VV_VF_RM;
defm PseudoVFWNMACC : VPseudoVWMAC_VV_VF_RM;
defm PseudoVFWMSAC : VPseudoVWMAC_VV_VF_RM;
Expand All @@ -6457,7 +6459,7 @@ defm PseudoVFWMACCBF16 : VPseudoVWMAC_VV_VF_BF_RM;
//===----------------------------------------------------------------------===//
// 13.8. Vector Floating-Point Square-Root Instruction
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true, hasSideEffects = 0 in
let mayRaiseFPException = true in
defm PseudoVFSQRT : VPseudoVSQR_V_RM;

//===----------------------------------------------------------------------===//
Expand All @@ -6469,7 +6471,7 @@ defm PseudoVFRSQRT7 : VPseudoVRCP_V;
//===----------------------------------------------------------------------===//
// 13.10. Vector Floating-Point Reciprocal Estimate Instruction
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true, hasSideEffects = 0 in
let mayRaiseFPException = true in
defm PseudoVFREC7 : VPseudoVRCP_V_RM;

//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -6519,29 +6521,23 @@ defm PseudoVFMV_V : VPseudoVMV_F;
// 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true in {
let hasSideEffects = 0 in {
defm PseudoVFCVT_XU_F : VPseudoVCVTI_V_RM;
defm PseudoVFCVT_X_F : VPseudoVCVTI_V_RM;
}

defm PseudoVFCVT_RTZ_XU_F : VPseudoVCVTI_V;
defm PseudoVFCVT_RTZ_X_F : VPseudoVCVTI_V;

defm PseudoVFROUND_NOEXCEPT : VPseudoVFROUND_NOEXCEPT_V;
let hasSideEffects = 0 in {
defm PseudoVFCVT_F_XU : VPseudoVCVTF_V_RM;
defm PseudoVFCVT_F_X : VPseudoVCVTF_V_RM;
}
} // mayRaiseFPException = true

//===----------------------------------------------------------------------===//
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true in {
let hasSideEffects = 0 in {
defm PseudoVFWCVT_XU_F : VPseudoVWCVTI_V_RM;
defm PseudoVFWCVT_X_F : VPseudoVWCVTI_V_RM;
}

defm PseudoVFWCVT_RTZ_XU_F : VPseudoVWCVTI_V;
defm PseudoVFWCVT_RTZ_X_F : VPseudoVWCVTI_V;
Expand All @@ -6557,23 +6553,17 @@ defm PseudoVFWCVTBF16_F_F : VPseudoVWCVTD_V;
// 13.19. Narrowing Floating-Point/Integer Type-Convert Instructions
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true in {
let hasSideEffects = 0 in {
defm PseudoVFNCVT_XU_F : VPseudoVNCVTI_W_RM;
defm PseudoVFNCVT_X_F : VPseudoVNCVTI_W_RM;
}

defm PseudoVFNCVT_RTZ_XU_F : VPseudoVNCVTI_W;
defm PseudoVFNCVT_RTZ_X_F : VPseudoVNCVTI_W;

let hasSideEffects = 0 in {
defm PseudoVFNCVT_F_XU : VPseudoVNCVTF_W_RM;
defm PseudoVFNCVT_F_X : VPseudoVNCVTF_W_RM;
}

let hasSideEffects = 0 in {
defm PseudoVFNCVT_F_F : VPseudoVNCVTD_W_RM;
defm PseudoVFNCVTBF16_F_F : VPseudoVNCVTD_W_RM;
}

defm PseudoVFNCVT_ROD_F_F : VPseudoVNCVTD_W;
} // mayRaiseFPException = true
Expand Down Expand Up @@ -6609,19 +6599,17 @@ let Predicates = [HasVInstructionsAnyF] in {
//===----------------------------------------------------------------------===//
// 14.3. Vector Single-Width Floating-Point Reduction Instructions
//===----------------------------------------------------------------------===//
let mayRaiseFPException = true, hasSideEffects = 0 in {
let mayRaiseFPException = true in {
defm PseudoVFREDOSUM : VPseudoVFREDO_VS_RM;
defm PseudoVFREDUSUM : VPseudoVFRED_VS_RM;
}
let mayRaiseFPException = true in {
defm PseudoVFREDMIN : VPseudoVFREDMINMAX_VS;
defm PseudoVFREDMAX : VPseudoVFREDMINMAX_VS;
}

//===----------------------------------------------------------------------===//
// 14.4. Vector Widening Floating-Point Reduction Instructions
//===----------------------------------------------------------------------===//
let IsRVVWideningReduction = 1, hasSideEffects = 0, mayRaiseFPException = true in {
let IsRVVWideningReduction = 1, mayRaiseFPException = true in {
defm PseudoVFWREDUSUM : VPseudoVFWRED_VS_RM;
defm PseudoVFWREDOSUM : VPseudoVFWREDO_VS_RM;
}
Expand Down
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