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Merged
merged 6 commits into from
Apr 14, 2025
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[RegAlloc] Sort CopyHint by IsCSR #131046

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a567100
[RegAlloc] Sort CopyHint by IsCSR
michaelmaitland Mar 12, 2025
78dc8f8
Precommit test case
michaelmaitland Mar 13, 2025
0d0ad25
fixup! add test
michaelmaitland Mar 28, 2025
25deaf7
fixup! test case change
michaelmaitland Mar 28, 2025
6ef87cd
fixup! cleanup
michaelmaitland Mar 31, 2025
76f0138
fixup! fix test run line
michaelmaitland Mar 31, 2025
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13 changes: 10 additions & 3 deletions llvm/lib/CodeGen/CalcSpillWeights.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -210,13 +210,18 @@ float VirtRegAuxInfo::weightCalcHelper(LiveInterval &LI, SlotIndex *Start,
struct CopyHint {
Register Reg;
float Weight;
CopyHint(Register R, float W) : Reg(R), Weight(W) {}
bool IsCSR;
CopyHint(Register R, float W, bool IsCSR)
: Reg(R), Weight(W), IsCSR(IsCSR) {}
bool operator<(const CopyHint &Rhs) const {
// Always prefer any physreg hint.
if (Reg.isPhysical() != Rhs.Reg.isPhysical())
return Reg.isPhysical();
if (Weight != Rhs.Weight)
return (Weight > Rhs.Weight);
// Prefer non-CSR to CSR.
if (Reg.isPhysical() && IsCSR != Rhs.IsCSR)
return !IsCSR;
return Reg.id() < Rhs.Reg.id(); // Tie-breaker.
}
};
Expand Down Expand Up @@ -299,10 +304,12 @@ float VirtRegAuxInfo::weightCalcHelper(LiveInterval &LI, SlotIndex *Start,
SmallVector<CopyHint, 8> RegHints;
for (const auto &[Reg, Weight] : Hint) {
if (Reg != SkipReg)
RegHints.emplace_back(Reg, Weight);
RegHints.emplace_back(
Reg, Weight,
Reg.isPhysical() ? TRI.isCalleeSavedPhysReg(Reg, MF) : false);
}
sort(RegHints);
for (const auto &[Reg, Weight] : RegHints)
for (const auto &[Reg, _, __] : RegHints)
MRI.addRegAllocationHint(LI.reg(), Reg);

// Weakly boost the spill weight of hinted registers.
Expand Down
10 changes: 3 additions & 7 deletions llvm/test/CodeGen/AArch64/aarch64-signedreturnaddress.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -15,10 +15,8 @@ entry:
; CHECK-NEXT: mov x0, x30
; CHECK-NEXT: ldr x30, [sp], #16
; CHECK-NEXT: ret
; CHECKV83: str x30, [sp, #-16]!
; CHECKV83-NEXT: xpaci x30
; CHECKV83-NEXT: mov x0, x30
; CHECKV83-NEXT: ldr x30, [sp], #16
; CHECKV83: mov x0, x30
; CHECKV83-NEXT: xpaci x0
; CHECKV83-NEXT: ret
%0 = tail call ptr @llvm.returnaddress(i32 0)
ret ptr %0
Expand All @@ -35,10 +33,8 @@ entry:
; CHECK-NEXT: hint #29
; CHECK-NEXT: ret
; CHECKV83: paciasp
; CHECKV83-NEXT: str x30, [sp, #-16]!
; CHECKV83-NEXT: xpaci x30
; CHECKV83-NEXT: mov x0, x30
; CHECKV83-NEXT: ldr x30, [sp], #16
; CHECKV83-NEXT: xpaci x0
; CHECKV83-NEXT: retaa
%0 = tail call ptr @llvm.returnaddress(i32 0)
ret ptr %0
Expand Down
22 changes: 22 additions & 0 deletions llvm/test/CodeGen/AArch64/csr-copy-hint.mir
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@@ -0,0 +1,22 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=arm64-eabi -mattr=v8.3a \ -stop-after=virtregmap -o - %s | FileCheck %s
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@arsenm arsenm Mar 28, 2025

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Suggested change
# RUN: llc -mtriple=arm64-eabi -mattr=v8.3a \ -stop-after=virtregmap -o - %s | FileCheck %s
# RUN: llc -mtriple=arm64-eabi -mattr=v8.3a -stop-after=virtregmap -o - %s | FileCheck %s

I'm not sure what this run line does, but it probably should be an error. What is the starting point?

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@michaelmaitland michaelmaitland Mar 28, 2025

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Sorry, that was an artifact I forgot to remove when I had the run line on multiple lines. Removed


---
name: ra0
tracksRegLiveness: true
isSSA: true
body: |
bb.0.entry:
liveins: $lr

; CHECK-LABEL: name: ra0
; CHECK: liveins: $lr
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x0 = ORRXrs $xzr, $lr, 0
; CHECK-NEXT: renamable $x0 = XPACI killed renamable $x0
; CHECK-NEXT: RET undef $lr, implicit killed $x0
%0:gpr64 = COPY killed $lr
%1:gpr64 = XPACI killed %0
$x0 = COPY killed %1
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@michaelmaitland michaelmaitland Mar 28, 2025

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@arsenm how is this?

RET_ReallyLR implicit killed $x0
...
7 changes: 2 additions & 5 deletions llvm/test/CodeGen/AArch64/ptrauth-ret.ll
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Expand Up @@ -112,12 +112,9 @@ define void @test_noframe() #0 {
define ptr @test_returnaddress_0() #0 {
; CHECK-LABEL: test_returnaddress_0:
; CHECK: %bb.0:
; CHECK-NEXT: pacibsp
; CHECK-NEXT: str x30, [sp, #-16]!
; CHECK-NEXT: xpaci x30
; CHECK-NEXT: mov x0, x30
; CHECK-NEXT: ldr x30, [sp], #16
; CHECK-NEXT: retab
; CHECK-NEXT: xpaci x0
; CHECK-NEXT: ret
%r = call ptr @llvm.returnaddress(i32 0)
ret ptr %r
}
Expand Down
30 changes: 30 additions & 0 deletions llvm/test/CodeGen/AArch64/sort-copy-hints.mir
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@@ -0,0 +1,30 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc %s -passes=greedy -mtriple=aarch64 | FileCheck %s

---
name: ra0
tracksRegLiveness: true
noPhis: true
liveins:
- { reg: '$lr', virtual-reg: '%0' }
body: |
bb.0.entry:
liveins: $lr

; CHECK-LABEL: name: ra0
; CHECK: liveins: $lr
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $lr
; CHECK-NEXT: $lr = COPY [[COPY]]
; CHECK-NEXT: XPACLRI implicit-def $lr, implicit $lr
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64all = COPY $lr
; CHECK-NEXT: $x0 = COPY [[COPY1]]
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:gpr64 = COPY $lr
$lr = COPY %0
XPACLRI implicit-def $lr, implicit $lr
%1:gpr64all = COPY $lr
$x0 = COPY %1
RET_ReallyLR implicit killed $x0

...
6 changes: 2 additions & 4 deletions llvm/test/CodeGen/AVR/calling-conv/c/basic_aggr.ll
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Expand Up @@ -132,17 +132,15 @@ define i8 @foo2([6 x i8] %0, [6 x i8] %1, [6 x i8] %2) {
define i8 @foo3([9 x i8] %0, [9 x i8] %1) {
; CHECK-LABEL: foo3:
; CHECK: ; %bb.0:
; CHECK-NEXT: push r16
; CHECK-NEXT: push r28
; CHECK-NEXT: push r29
; CHECK-NEXT: in r28, 61
; CHECK-NEXT: in r29, 62
; CHECK-NEXT: ldd r24, Y+6
; CHECK-NEXT: sub r16, r24
; CHECK-NEXT: mov r24, r16
; CHECK-NEXT: ldd r25, Y+5
; CHECK-NEXT: sub r24, r25
; CHECK-NEXT: pop r29
; CHECK-NEXT: pop r28
; CHECK-NEXT: pop r16
; CHECK-NEXT: ret
%3 = extractvalue [9 x i8] %0, 0
%4 = extractvalue [9 x i8] %1, 0
Expand Down
16 changes: 7 additions & 9 deletions llvm/test/CodeGen/AVR/calling-conv/c/stack.ll
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Expand Up @@ -74,17 +74,15 @@ define i8 @foo1([19 x i8] %a, i8 %b) {
define i8 @foo2([17 x i8] %a, i8 %b) {
; CHECK-LABEL: foo2:
; CHECK: ; %bb.0:
; CHECK-NEXT: push r8
; CHECK-NEXT: push r28
; CHECK-NEXT: push r29
; CHECK-NEXT: in r28, 61
; CHECK-NEXT: in r29, 62
; CHECK-NEXT: ldd r24, Y+6
; CHECK-NEXT: sub r8, r24
; CHECK-NEXT: mov r24, r8
; CHECK-NEXT: pop r29
; CHECK-NEXT: pop r28
; CHECK-NEXT: pop r8
; CHECK-NEXT: in r28, 61
; CHECK-NEXT: in r29, 62
; CHECK-NEXT: mov r24, r8
; CHECK-NEXT: ldd r25, Y+5
; CHECK-NEXT: sub r24, r25
; CHECK-NEXT: pop r29
; CHECK-NEXT: pop r28
; CHECK-NEXT: ret
%c = extractvalue [17 x i8] %a, 0
%d = sub i8 %c, %b
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/AVR/dynalloca.ll
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Expand Up @@ -64,16 +64,16 @@ define void @dynalloca2(i16 %x) {
; CHECK-NEXT: out 63, r0
; CHECK-NEXT: out 61, {{.*}}
; Store values on the stack
; CHECK: ldi r16, 0
; CHECK: ldi r17, 0
; CHECK: std Z+8, r17
; CHECK: std Z+7, r16
; CHECK: std Z+6, r17
; CHECK: std Z+5, r16
; CHECK: std Z+4, r17
; CHECK: std Z+3, r16
; CHECK: std Z+2, r17
; CHECK: std Z+1, r16
; CHECK: ldi r20, 0
; CHECK: ldi r21, 0
; CHECK: std Z+8, r21
; CHECK: std Z+7, r20
; CHECK: std Z+6, r21
; CHECK: std Z+5, r20
; CHECK: std Z+4, r21
; CHECK: std Z+3, r20
; CHECK: std Z+2, r21
; CHECK: std Z+1, r20
; CHECK: call
; Call frame restore
; CHECK-NEXT: in r30, 61
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AVR/return.ll
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Expand Up @@ -126,8 +126,8 @@ define i32 @return32_arg(i32 %x) {
define i32 @return32_arg2(i32 %x, i32 %y, i32 %z) {
; AVR-LABEL: return32_arg2:
; AVR: ; %bb.0:
; AVR-NEXT: movw r22, r14
; AVR-NEXT: movw r24, r16
; AVR-NEXT: movw r22, r14
; AVR-NEXT: ret
;
; TINY-LABEL: return32_arg2:
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
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Expand Up @@ -60,7 +60,7 @@ entry:
;CHECK: sethi
;CHECK: !NO_APP
;CHECK-NEXT: ble
;CHECK-NEXT: mov
;CHECK-NEXT: nop
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@michaelmaitland michaelmaitland Mar 13, 2025

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This test is still correct. The mov got hoisted and isn't relevant to this test anymore. There is a nop here now which is the point of this test (an instruction is placed in the delay slot).

tail call void asm sideeffect "sethi 0, %g0", ""() nounwind
%0 = icmp slt i32 %a, 0
br i1 %0, label %bb, label %bb1
Expand Down
40 changes: 20 additions & 20 deletions llvm/test/CodeGen/SPARC/32abi.ll
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Expand Up @@ -143,28 +143,28 @@ define double @floatarg(double %a0, ; %i0,%i1
; CHECK-LABEL: call_floatarg:
; HARD: save %sp, -112, %sp
; HARD: mov %i2, %o1
; HARD-NEXT: mov %i0, %o2
; HARD-NEXT: mov %i1, %o0
; HARD-NEXT: st %i0, [%sp+104]
; HARD-NEXT: std %o0, [%sp+96]
; HARD-NEXT: st %o1, [%sp+92]
; HARD-NEXT: mov %i0, %o2
; HARD-NEXT: mov %i1, %o3
; HARD-NEXT: mov %o1, %o4
; HARD-NEXT: mov %i1, %o5
; HARD-NEXT: call floatarg
; HARD: std %f0, [%i4]
; SOFT: st %i0, [%sp+104]
; SOFT-NEXT: st %i2, [%sp+100]
; SOFT-NEXT: st %i1, [%sp+96]
; SOFT-NEXT: st %i2, [%sp+92]
; SOFT-NEXT: mov %i1, %o0
; SOFT-NEXT: mov %i2, %o1
; SOFT-NEXT: mov %i0, %o2
; SOFT-NEXT: mov %i1, %o3
; SOFT-NEXT: mov %i2, %o4
; SOFT-NEXT: mov %i1, %o5
; SOFT-NEXT: call floatarg
; SOFT: std %o0, [%i4]
; SOFT: mov %i2, %o1
; SOFT-NEXT: mov %i1, %o0
; SOFT-NEXT: mov %i0, %o2
; SOFT-NEXT: st %i0, [%sp+104]
; SOFT-NEXT: st %i2, [%sp+100]
; SOFT-NEXT: st %i1, [%sp+96]
; SOFT-NEXT: st %i2, [%sp+92]
; SOFT-NEXT: mov %i1, %o3
; SOFT-NEXT: mov %i2, %o4
; SOFT-NEXT: mov %i1, %o5
; SOFT-NEXT: call floatarg
; SOFT: std %o0, [%i4]
; CHECK: restore
define void @call_floatarg(float %f1, double %d2, float %f5, ptr %p) {
%r = call double @floatarg(double %d2, float %f1, double %d2, double %d2,
Expand Down Expand Up @@ -228,16 +228,16 @@ define i64 @i64arg(i64 %a0, ; %i0,%i1

; CHECK-LABEL: call_i64arg:
; CHECK: save %sp, -112, %sp
; CHECK: st %i0, [%sp+104]
; CHECK: mov %i2, %o1
; CHECK-NEXT: mov %i1, %o0
; CHECK-NEXT: mov %i0, %o2
; CHECK-NEXT: st %i0, [%sp+104]
; CHECK-NEXT: st %i2, [%sp+100]
; CHECK-NEXT: st %i1, [%sp+96]
; CHECK-NEXT: st %i2, [%sp+92]
; CHECK-NEXT: mov %i1, %o0
; CHECK-NEXT: mov %i2, %o1
; CHECK-NEXT: mov %i0, %o2
; CHECK-NEXT: mov %i1, %o3
; CHECK-NEXT: mov %i2, %o4
; CHECK-NEXT: mov %i1, %o5
; CHECK-NEXT: mov %i1, %o3
; CHECK-NEXT: mov %i2, %o4
; CHECK-NEXT: mov %i1, %o5
; CHECK-NEXT: call i64arg
; CHECK: std %o0, [%i3]
; CHECK-NEXT: restore
Expand Down
14 changes: 5 additions & 9 deletions llvm/test/CodeGen/SPARC/64abi.ll
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Expand Up @@ -118,12 +118,10 @@ define double @floatarg(float %a0, ; %f1
; SOFT: stx %i2, [%sp+2239]
; SOFT: stx %i2, [%sp+2231]
; SOFT: stx %i2, [%sp+2223]
; SOFT: mov %i2, %o0
; SOFT: mov %i1, %o1
; SOFT: mov %i1, %o2
; SOFT: mov %i1, %o3
; SOFT: mov %i2, %o4
; SOFT: mov %i2, %o5
; SOFT: mov %i1, %o2
; SOFT: mov %i1, %o3
; SOFT: mov %i2, %o4
; SOFT: mov %i2, %o5
; CHECK: call floatarg
; CHECK-NOT: add %sp
; CHECK: restore
Expand Down Expand Up @@ -174,11 +172,9 @@ define void @mixedarg(i8 %a0, ; %i0

; CHECK-LABEL: call_mixedarg:
; CHECK: stx %i2, [%sp+2247]
; SOFT: stx %i1, [%sp+2239]
; CHECK: stx %i0, [%sp+2223]
; HARD: fmovd %f2, %f6
; HARD: fmovd %f2, %f16
; SOFT: mov %i1, %o3
; CHECK: call mixedarg
; CHECK-NOT: add %sp
; CHECK: restore
Expand Down Expand Up @@ -262,8 +258,8 @@ define i32 @inreg_if(float inreg %a0, ; %f0
}

; CHECK-LABEL: call_inreg_if:
; HARD: fmovs %f3, %f0
; HARD: mov %i2, %o0
; HARD: fmovs %f3, %f0
; SOFT: srl %i2, 0, %i0
; SOFT: sllx %i1, 32, %i1
; SOFT: or %i1, %i0, %o0
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/SPARC/bigreturn.ll
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Expand Up @@ -92,9 +92,9 @@ define i32 @call_ret_i32_arr(i32 %0) {
; SPARC-NEXT: .cfi_def_cfa_register %fp
; SPARC-NEXT: .cfi_window_save
; SPARC-NEXT: .cfi_register %o7, %i7
; SPARC-NEXT: add %fp, -64, %i1
; SPARC-NEXT: st %i1, [%sp+64]
; SPARC-NEXT: mov %i0, %o0
; SPARC-NEXT: add %fp, -64, %i0
; SPARC-NEXT: st %i0, [%sp+64]
; SPARC-NEXT: call ret_i32_arr
; SPARC-NEXT: nop
; SPARC-NEXT: unimp 64
Expand All @@ -110,8 +110,8 @@ define i32 @call_ret_i32_arr(i32 %0) {
; SPARC64-NEXT: .cfi_def_cfa_register %fp
; SPARC64-NEXT: .cfi_window_save
; SPARC64-NEXT: .cfi_register %o7, %i7
; SPARC64-NEXT: add %fp, 1983, %o0
; SPARC64-NEXT: mov %i0, %o1
; SPARC64-NEXT: add %fp, 1983, %o0
; SPARC64-NEXT: call ret_i32_arr
; SPARC64-NEXT: nop
; SPARC64-NEXT: ld [%fp+2043], %i0
Expand Down Expand Up @@ -220,10 +220,10 @@ define i64 @call_ret_i64_arr(i64 %0) {
; SPARC-NEXT: .cfi_def_cfa_register %fp
; SPARC-NEXT: .cfi_window_save
; SPARC-NEXT: .cfi_register %o7, %i7
; SPARC-NEXT: add %fp, -128, %i2
; SPARC-NEXT: st %i2, [%sp+64]
; SPARC-NEXT: mov %i0, %o0
; SPARC-NEXT: mov %i1, %o1
; SPARC-NEXT: mov %i0, %o0
; SPARC-NEXT: add %fp, -128, %i0
; SPARC-NEXT: st %i0, [%sp+64]
; SPARC-NEXT: call ret_i64_arr
; SPARC-NEXT: nop
; SPARC-NEXT: unimp 128
Expand All @@ -239,8 +239,8 @@ define i64 @call_ret_i64_arr(i64 %0) {
; SPARC64-NEXT: .cfi_def_cfa_register %fp
; SPARC64-NEXT: .cfi_window_save
; SPARC64-NEXT: .cfi_register %o7, %i7
; SPARC64-NEXT: add %fp, 1919, %o0
; SPARC64-NEXT: mov %i0, %o1
; SPARC64-NEXT: add %fp, 1919, %o0
; SPARC64-NEXT: call ret_i64_arr
; SPARC64-NEXT: nop
; SPARC64-NEXT: ldx [%fp+2039], %i0
Expand Down
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