[RegAlloc] Sort CopyHint by IsCSR

llvm/test/CodeGen/AArch64/csr-copy-hint.mir

@@ -0,0 +1,22 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=arm64-eabi -mattr=v8.3a \ -stop-after=virtregmap -o - %s | FileCheck %s
+
+---
+name:            ra0
+tracksRegLiveness: true
+isSSA:           true
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; CHECK-LABEL: name: ra0
+    ; CHECK: liveins: $lr
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: $x0 = ORRXrs $xzr, $lr, 0
+    ; CHECK-NEXT: renamable $x0 = XPACI killed renamable $x0
+    ; CHECK-NEXT: RET undef $lr, implicit killed $x0
+    %0:gpr64 = COPY killed $lr
+    %1:gpr64 = XPACI killed %0
+    $x0 = COPY killed %1
+    RET_ReallyLR implicit killed $x0
+...

llvm/test/CodeGen/AArch64/sort-copy-hints.mir

@@ -0,0 +1,30 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc %s -passes=greedy -mtriple=aarch64 | FileCheck %s
+
+---
+name:            ra0
+tracksRegLiveness: true
+noPhis:          true
+liveins:
+  - { reg: '$lr', virtual-reg: '%0' }
+body:             |
+  bb.0.entry:
+    liveins: $lr
+
+    ; CHECK-LABEL: name: ra0
+    ; CHECK: liveins: $lr
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $lr
+    ; CHECK-NEXT: $lr = COPY [[COPY]]
+    ; CHECK-NEXT: XPACLRI implicit-def $lr, implicit $lr
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64all = COPY $lr
+    ; CHECK-NEXT: $x0 = COPY [[COPY1]]
+    ; CHECK-NEXT: RET_ReallyLR implicit $x0
+    %0:gpr64 = COPY $lr
+    $lr = COPY %0
+    XPACLRI implicit-def $lr, implicit $lr
+    %1:gpr64all = COPY $lr
+    $x0 = COPY %1
+    RET_ReallyLR implicit killed $x0
+
+...