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[AArch64][CodeGen] Add patterns for +lsfe atomic stores #131174

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[AArch64][CodeGen] Add patterns for +lsfe atomic stores #131174

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ba0dc8f
Update generate-tests.py script to add +lsfe atomicrmw tests where the
kmclaughlin-arm Feb 13, 2025
aaefe4b
[AArch64] Add patterns for +lsfe atomic stores
kmclaughlin-arm Feb 13, 2025
d92da0a
- Fix formatting issues in generate-tests.py
kmclaughlin-arm Mar 13, 2025
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12 changes: 6 additions & 6 deletions llvm/lib/Target/AArch64/AArch64InstrAtomics.td
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Original file line number Diff line number Diff line change
Expand Up @@ -548,13 +548,13 @@ defm atomic_load_fmin : binary_atomic_op_fp<atomic_load_fmin>;
defm atomic_load_fmax : binary_atomic_op_fp<atomic_load_fmax>;

let Predicates = [HasLSFE] in {
defm : LDFPOPregister_patterns<"LDFADD", "atomic_load_fadd">;
defm : LDFPOPregister_patterns<"LDFMAXNM", "atomic_load_fmax">;
defm : LDFPOPregister_patterns<"LDFMINNM", "atomic_load_fmin">;
defm : LDFPOPregister_patterns<"FADD", "atomic_load_fadd">;
defm : LDFPOPregister_patterns<"FMAXNM", "atomic_load_fmax">;
defm : LDFPOPregister_patterns<"FMINNM", "atomic_load_fmin">;

defm : LDBFPOPregister_patterns<"LDBFADD", "atomic_load_fadd">;
defm : LDBFPOPregister_patterns<"LDBFMAXNM", "atomic_load_fmax">;
defm : LDBFPOPregister_patterns<"LDBFMINNM", "atomic_load_fmin">;
defm : LDBFPOPregister_patterns<"BFADD", "atomic_load_fadd">;
defm : LDBFPOPregister_patterns<"BFMAXNM", "atomic_load_fmax">;
defm : LDBFPOPregister_patterns<"BFMINNM", "atomic_load_fmin">;
}

// v8.9a/v9.4a FEAT_LRCPC patterns
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32 changes: 26 additions & 6 deletions llvm/lib/Target/AArch64/AArch64InstrFormats.td
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Expand Up @@ -12493,19 +12493,39 @@ multiclass LDOPregister_patterns_mod<string inst, string op, string mod> {
(i32 (!cast<Instruction>(mod#Wrr) WZR, GPR32:$Rm))>;
}

class AtomicStoreMonotonicFrag<SDNode atomic_op> : PatFrag<
(ops node:$ptr, node:$value),
(atomic_op node:$ptr, node:$value),
[{ return SDValue(N, 0).use_empty() &&
cast<AtomicSDNode>(N)->getMergedOrdering() == AtomicOrdering::Monotonic; }]>;

class AtomicStoreReleaseFrag<SDNode atomic_op> : PatFrag<
(ops node:$ptr, node:$value),
(atomic_op node:$ptr, node:$value),
[{ return SDValue(N, 0).use_empty() &&
cast<AtomicSDNode>(N)->getMergedOrdering() == AtomicOrdering::Release; }]>;

let Predicates = [HasLSFE] in
multiclass LDFPOPregister_patterns_ord_dag<string inst, string suffix, string op,
ValueType vt, dag data> {
ValueType vt, dag data> {
def : Pat<(!cast<PatFrag>(op#"_"#vt#"_monotonic") FPR64:$Rn, data),
(!cast<Instruction>(inst # suffix) data, FPR64:$Rn)>;
(!cast<Instruction>("LD" # inst # suffix) data, FPR64:$Rn)>;
def : Pat<(!cast<PatFrag>(op#"_"#vt#"_acquire") FPR64:$Rn, data),
(!cast<Instruction>(inst # "A" # suffix) data, FPR64:$Rn)>;
(!cast<Instruction>("LD" # inst # "A" # suffix) data, FPR64:$Rn)>;
def : Pat<(!cast<PatFrag>(op#"_"#vt#"_release") FPR64:$Rn, data),
(!cast<Instruction>(inst # "L" # suffix) data, FPR64:$Rn)>;
(!cast<Instruction>("LD" # inst # "L" # suffix) data, FPR64:$Rn)>;
def : Pat<(!cast<PatFrag>(op#"_"#vt#"_acq_rel") FPR64:$Rn, data),
(!cast<Instruction>(inst # "AL" # suffix) data, FPR64:$Rn)>;
(!cast<Instruction>("LD" # inst # "AL" # suffix) data, FPR64:$Rn)>;
def : Pat<(!cast<PatFrag>(op#"_"#vt#"_seq_cst") FPR64:$Rn, data),
(!cast<Instruction>(inst # "AL" # suffix) data, FPR64:$Rn)>;
(!cast<Instruction>("LD" # inst # "AL" # suffix) data, FPR64:$Rn)>;

let AddedComplexity = 5 in {
def : Pat<(AtomicStoreMonotonicFrag<!cast<SDNode>(op)> FPR64:$Rn, data),
(!cast<Instruction>("ST" # inst # suffix) data, FPR64:$Rn)>;

def : Pat<(AtomicStoreReleaseFrag<!cast<SDNode>(op)> FPR64:$Rn, data),
(!cast<Instruction>("ST" # inst # "L" # suffix) data, FPR64:$Rn)>;
}
}

multiclass LDFPOPregister_patterns_ord<string inst, string suffix, string op,
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