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SelectionDAG: neg (and x, 1) --> SIGN_EXTEND_INREG x, i1 #131239

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Merged
merged 1 commit into from
Mar 14, 2025
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SelectionDAG: neg (and x, 1) --> SIGN_EXTEND_INREG x, i1 #131239

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14 changes: 14 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3964,6 +3964,20 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
isNullConstant(N1S.getOperand(0)))
return DAG.getSplat(VT, DL, N1S.getOperand(1));
}

// sub 0, (and x, 1) --> SIGN_EXTEND_INREG x, i1
if (N1.getOpcode() == ISD::AND && N1.hasOneUse() &&
isOneOrOneSplat(N1->getOperand(1))) {
EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), 1);
if (VT.isVector())
ExtVT = EVT::getVectorVT(*DAG.getContext(), ExtVT,
VT.getVectorElementCount());
if (TLI.getOperationAction(ISD::SIGN_EXTEND_INREG, ExtVT) ==
TargetLowering::Legal) {
return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, N1->getOperand(0),
DAG.getValueType(ExtVT));
}
}
}

// Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1)
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15 changes: 15 additions & 0 deletions llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll
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Expand Up @@ -1067,3 +1067,18 @@ if.else:
end:
ret void
}

define i64 @sign_extend_lsb(i64 %arg) nounwind {
; LLC-LABEL: sign_extend_lsb:
; LLC: // %bb.0:
; LLC-NEXT: sbfx x0, x0, #0, #1
; LLC-NEXT: ret
; OPT-LABEL: @sign_extend_lsb(
; OPT-NEXT: [[AND:%.*]] = and i64 [[ARG:%.*]], 1
; OPT-NEXT: [[NEG:%.*]] = sub i64 0, [[AND]]
; OPT-NEXT: ret i64 [[NEG]]
;
%and = and i64 %arg, 1
%neg = sub i64 0, %and
ret i64 %neg
}
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AArch64/pr61111.ll
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Expand Up @@ -5,9 +5,9 @@ define i62 @f(i1 %0) {
; CHECK-LABEL: f:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
; CHECK-NEXT: and x8, x0, #0x1
; CHECK-NEXT: sub x8, x8, #1
; CHECK-NEXT: tst x8, #0x3fffffffffffffff
; CHECK-NEXT: sbfx x8, x0, #0, #1
; CHECK-NEXT: mov x9, #4611686018427387903 // =0x3fffffffffffffff
; CHECK-NEXT: bics xzr, x9, x8
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
%2 = zext i1 %0 to i59
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