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[AMDGPU] Fix register class constraints for si-fold-operands pass when folding immediate into copies #131387

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Merged
merged 6 commits into from
Apr 30, 2025
Merged

[AMDGPU] Fix register class constraints for si-fold-operands pass when folding immediate into copies #131387

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e2e886d
[AMDGPU] Fix register class constraints for si-fold-operands pass
mssefat Mar 14, 2025
26a3099
Removed changes for fold-imm-copy.mir and created a nfc for it with a…
mssefat Apr 15, 2025
547d52f
Fixes #130020
mssefat Apr 15, 2025
e655bd6
[AMDGPU] Fix register class constraints for si-fold-operands pass
mssefat Apr 16, 2025
ec4ad28
Reverting to previous approach of using DestRC->hasSuperClassEq(ResRC)
mssefat Apr 30, 2025
a73c5ee
Formatted SIFoldOperands.cpp
mssefat Apr 30, 2025
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14 changes: 14 additions & 0 deletions llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1068,6 +1068,20 @@ void SIFoldOperandsImpl::foldOperand(
if (MovOp == AMDGPU::COPY)
return;

// Check for common register subclass between destination (DestRC) and MOV
// result (ResRC). If exists, verify this common subclass is a superclass of
// (or equal to) the destination register class, otherwise folding is
// illegal.

const MCInstrDesc &MovDesc = TII->get(MovOp);
assert(MovDesc.getNumDefs() > 0 && MovDesc.operands()[0].RegClass != -1);
const TargetRegisterClass *ResRC =
TRI->getRegClass(MovDesc.operands()[0].RegClass);
const TargetRegisterClass *CommonRC = TRI->getCommonSubClass(DestRC, ResRC);

if (!CommonRC || !DestRC->hasSuperClassEq(CommonRC))
return;

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@arsenm arsenm Apr 18, 2025

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Suggested change
if (!CommonRC || !DestRC->hasSuperClassEq(CommonRC))
return;
if (!CommonRC)
return;

hasSuperClassEq should be redundant with finding the common class

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@mssefat mssefat Apr 21, 2025 •
edited
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I think hasSuperClassEq is not redundant with finding common subclass. Consider this basic block where the copy operation is illegal:

bb.0:
  %1:av_32 = V_MOV_B32_e32 32, implicit $exec
  $agpr0 = COPY %1:av_32
  S_ENDPGM 0

In this example:

DestRC is AV_32
ResRC is VGPR_32
CommonRC is VGPR_32

If we only check for CommonRC, the check would allow folding in this case since CommonRC exists (VGPR_32). However, folding here is illegal. And I think we need the condition if (!DestRC->hasSuperClassEq(CommonRC)) return;.

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@jayfoad jayfoad Apr 29, 2025

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Why do you need CommonRC? Isn't the whole check equivalent to DestRC->hasSuperClassEq(ResRC)?

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@jayfoad jayfoad Apr 29, 2025

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The code as you have written it is weird, because CommonRC is by construction a subclass of DestRC, and then you are checking that it is a superclass of DestRC. These can only both be true if CommonRC is DestRC.

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@mssefat mssefat Apr 30, 2025

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They should be equivalent check. I am reverting to the previous use of DestRC->hasSuperClassEq(ResRC). @arsenm please let me know if I am missing something.

MachineInstr::mop_iterator ImpOpI = UseMI->implicit_operands().begin();
MachineInstr::mop_iterator ImpOpE = UseMI->implicit_operands().end();
while (ImpOpI != ImpOpE) {
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116 changes: 67 additions & 49 deletions llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
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Expand Up @@ -202,52 +202,70 @@ body: |

...

# FIXME: Register class restrictions of av register not respected,
# issue 130020

# ---
# name: s_mov_b32_inlineimm_copy_s_to_av_32
# tracksRegLiveness: true
# body: |
# bb.0:
# %0:sreg_32 = S_MOV_B32 32
# %1:av_32 = COPY %0
# $agpr0 = COPY %1
# S_ENDPGM 0

# ...

# ---
# name: v_mov_b32_inlineimm_copy_v_to_av_32
# tracksRegLiveness: true
# body: |
# bb.0:
# %0:vgpr_32 = V_MOV_B32_e32 32, implicit $exec
# %1:av_32 = COPY %0
# $agpr0 = COPY %1
# S_ENDPGM 0
# ...

# ---
# name: s_mov_b32_imm_literal_copy_s_to_av_32
# tracksRegLiveness: true
# body: |
# bb.0:
# %0:sreg_32 = S_MOV_B32 999
# %1:av_32 = COPY %0
# $agpr0 = COPY %1
# S_ENDPGM 0

# ...

# ---
# name: v_mov_b32_imm_literal_copy_v_to_av_32
# tracksRegLiveness: true
# body: |
# bb.0:
# %0:vgpr_32 = V_MOV_B32_e32 999, implicit $exec
# %1:av_32 = COPY %0
# $agpr0 = COPY %1
# S_ENDPGM 0

# ...
---
name: s_mov_b32_inlineimm_copy_s_to_av_32
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@jayfoad jayfoad Mar 17, 2025

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New tests need checks for the expected output. Maybe convert the while file to use update_mir_test_checks?

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@mssefat mssefat Mar 26, 2025

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I have pushed the updated changes. Could you please review?

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@mssefat mssefat Apr 7, 2025

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Ping

tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: s_mov_b32_inlineimm_copy_s_to_av_32
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32
; GCN-NEXT: [[COPY:%[0-9]+]]:av_32 = COPY [[S_MOV_B32_]]
; GCN-NEXT: $agpr0 = COPY [[COPY]]
; GCN-NEXT: S_ENDPGM 0
%0:sreg_32 = S_MOV_B32 32
%1:av_32 = COPY %0
$agpr0 = COPY %1
S_ENDPGM 0

...

---
name: v_mov_b32_inlineimm_copy_v_to_av_32
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: v_mov_b32_inlineimm_copy_v_to_av_32
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 32, implicit $exec
; GCN-NEXT: [[COPY:%[0-9]+]]:av_32 = COPY [[V_MOV_B32_e32_]]
; GCN-NEXT: $agpr0 = COPY [[COPY]]
; GCN-NEXT: S_ENDPGM 0
%0:vgpr_32 = V_MOV_B32_e32 32, implicit $exec
%1:av_32 = COPY %0
$agpr0 = COPY %1
S_ENDPGM 0

...

---
name: s_mov_b32_imm_literal_copy_s_to_av_32
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: s_mov_b32_imm_literal_copy_s_to_av_32
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 999
; GCN-NEXT: [[COPY:%[0-9]+]]:av_32 = COPY [[S_MOV_B32_]]
; GCN-NEXT: $agpr0 = COPY [[COPY]]
; GCN-NEXT: S_ENDPGM 0
%0:sreg_32 = S_MOV_B32 999
%1:av_32 = COPY %0
$agpr0 = COPY %1
S_ENDPGM 0

...

---
name: v_mov_b32_imm_literal_copy_v_to_av_32
tracksRegLiveness: true
body: |
bb.0:
; GCN-LABEL: name: v_mov_b32_imm_literal_copy_v_to_av_32
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 999, implicit $exec
; GCN-NEXT: [[COPY:%[0-9]+]]:av_32 = COPY [[V_MOV_B32_e32_]]
; GCN-NEXT: $agpr0 = COPY [[COPY]]
; GCN-NEXT: S_ENDPGM 0
%0:vgpr_32 = V_MOV_B32_e32 999, implicit $exec
%1:av_32 = COPY %0
$agpr0 = COPY %1
S_ENDPGM 0

...
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