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[ARM,MVE] Change placeholder from undef to poison #131689

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Merged
merged 1 commit into from
Mar 18, 2025
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[ARM,MVE] Change placeholder from undef to poison #131689

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2 changes: 1 addition & 1 deletion clang/include/clang/Basic/arm_mve.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1537,7 +1537,7 @@ foreach desttype = T.All in {
let params = T.All in {
let pnt = PNT_None in {
def vcreateq: Intrinsic<Vector, (args u64:$a, u64:$b),
(vreinterpret (ielt_const (ielt_const (undef VecOf<u64>), $a, 0),
(vreinterpret (ielt_const (ielt_const (poison VecOf<u64>), $a, 0),
$b, 1), Vector)>;
def vuninitializedq: Intrinsic<Vector, (args), (undef Vector)>;
}
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1 change: 1 addition & 0 deletions clang/include/clang/Basic/arm_mve_defs.td
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Expand Up @@ -102,6 +102,7 @@ def int_min: CGHelperFn<"ARMMVEConstantSplat<1,0>">;
def int_max: CGHelperFn<"ARMMVEConstantSplat<0,1>">;
def uint_max: CGHelperFn<"ARMMVEConstantSplat<1,1>">;
def undef: IRFunction<"UndefValue::get">;
def poison: IRFunction<"PoisonValue::get">;
def icmp_eq: IRBuilder<"CreateICmpEQ">;
def icmp_ne: IRBuilder<"CreateICmpNE">;
def icmp_ugt: IRBuilder<"CreateICmpUGT">;
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36 changes: 18 additions & 18 deletions clang/test/CodeGen/arm-mve-intrinsics/admin.c
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Original file line number Diff line number Diff line change
Expand Up @@ -10,14 +10,14 @@

// CHECK-LE-LABEL: @test_vcreateq_f16(
// CHECK-LE-NEXT: entry:
// CHECK-LE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
// CHECK-LE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[A:%.*]], i64 0
// CHECK-LE-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
// CHECK-LE-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <8 x half>
// CHECK-LE-NEXT: ret <8 x half> [[TMP2]]
//
// CHECK-BE-LABEL: @test_vcreateq_f16(
// CHECK-BE-NEXT: entry:
// CHECK-BE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
// CHECK-BE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[A:%.*]], i64 0
// CHECK-BE-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
// CHECK-BE-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vreinterpretq.v8f16.v2i64(<2 x i64> [[TMP1]])
// CHECK-BE-NEXT: ret <8 x half> [[TMP2]]
Expand All @@ -29,14 +29,14 @@ float16x8_t test_vcreateq_f16(uint64_t a, uint64_t b)

// CHECK-LE-LABEL: @test_vcreateq_f32(
// CHECK-LE-NEXT: entry:
// CHECK-LE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
// CHECK-LE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[A:%.*]], i64 0
// CHECK-LE-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
// CHECK-LE-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <4 x float>
// CHECK-LE-NEXT: ret <4 x float> [[TMP2]]
//
// CHECK-BE-LABEL: @test_vcreateq_f32(
// CHECK-BE-NEXT: entry:
// CHECK-BE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
// CHECK-BE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[A:%.*]], i64 0
// CHECK-BE-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
// CHECK-BE-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vreinterpretq.v4f32.v2i64(<2 x i64> [[TMP1]])
// CHECK-BE-NEXT: ret <4 x float> [[TMP2]]
Expand All @@ -48,14 +48,14 @@ float32x4_t test_vcreateq_f32(uint64_t a, uint64_t b)

// CHECK-LE-LABEL: @test_vcreateq_s16(
// CHECK-LE-NEXT: entry:
// CHECK-LE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
// CHECK-LE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[A:%.*]], i64 0
// CHECK-LE-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
// CHECK-LE-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <8 x i16>
// CHECK-LE-NEXT: ret <8 x i16> [[TMP2]]
//
// CHECK-BE-LABEL: @test_vcreateq_s16(
// CHECK-BE-NEXT: entry:
// CHECK-BE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
// CHECK-BE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[A:%.*]], i64 0
// CHECK-BE-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
// CHECK-BE-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v2i64(<2 x i64> [[TMP1]])
// CHECK-BE-NEXT: ret <8 x i16> [[TMP2]]
Expand All @@ -67,14 +67,14 @@ int16x8_t test_vcreateq_s16(uint64_t a, uint64_t b)

// CHECK-LE-LABEL: @test_vcreateq_s32(
// CHECK-LE-NEXT: entry:
// CHECK-LE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
// CHECK-LE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[A:%.*]], i64 0
// CHECK-LE-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
// CHECK-LE-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <4 x i32>
// CHECK-LE-NEXT: ret <4 x i32> [[TMP2]]
//
// CHECK-BE-LABEL: @test_vcreateq_s32(
// CHECK-BE-NEXT: entry:
// CHECK-BE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
// CHECK-BE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[A:%.*]], i64 0
// CHECK-BE-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
// CHECK-BE-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vreinterpretq.v4i32.v2i64(<2 x i64> [[TMP1]])
// CHECK-BE-NEXT: ret <4 x i32> [[TMP2]]
Expand All @@ -86,7 +86,7 @@ int32x4_t test_vcreateq_s32(uint64_t a, uint64_t b)

// CHECK-LABEL: @test_vcreateq_s64(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
// CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[A:%.*]], i64 0
// CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
// CHECK-NEXT: ret <2 x i64> [[TMP1]]
//
Expand All @@ -97,14 +97,14 @@ int64x2_t test_vcreateq_s64(uint64_t a, uint64_t b)

// CHECK-LE-LABEL: @test_vcreateq_s8(
// CHECK-LE-NEXT: entry:
// CHECK-LE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
// CHECK-LE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[A:%.*]], i64 0
// CHECK-LE-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
// CHECK-LE-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <16 x i8>
// CHECK-LE-NEXT: ret <16 x i8> [[TMP2]]
//
// CHECK-BE-LABEL: @test_vcreateq_s8(
// CHECK-BE-NEXT: entry:
// CHECK-BE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
// CHECK-BE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[A:%.*]], i64 0
// CHECK-BE-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
// CHECK-BE-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vreinterpretq.v16i8.v2i64(<2 x i64> [[TMP1]])
// CHECK-BE-NEXT: ret <16 x i8> [[TMP2]]
Expand All @@ -116,14 +116,14 @@ int8x16_t test_vcreateq_s8(uint64_t a, uint64_t b)

// CHECK-LE-LABEL: @test_vcreateq_u16(
// CHECK-LE-NEXT: entry:
// CHECK-LE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
// CHECK-LE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[A:%.*]], i64 0
// CHECK-LE-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
// CHECK-LE-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <8 x i16>
// CHECK-LE-NEXT: ret <8 x i16> [[TMP2]]
//
// CHECK-BE-LABEL: @test_vcreateq_u16(
// CHECK-BE-NEXT: entry:
// CHECK-BE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
// CHECK-BE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[A:%.*]], i64 0
// CHECK-BE-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
// CHECK-BE-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v2i64(<2 x i64> [[TMP1]])
// CHECK-BE-NEXT: ret <8 x i16> [[TMP2]]
Expand All @@ -135,14 +135,14 @@ uint16x8_t test_vcreateq_u16(uint64_t a, uint64_t b)

// CHECK-LE-LABEL: @test_vcreateq_u32(
// CHECK-LE-NEXT: entry:
// CHECK-LE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
// CHECK-LE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[A:%.*]], i64 0
// CHECK-LE-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
// CHECK-LE-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <4 x i32>
// CHECK-LE-NEXT: ret <4 x i32> [[TMP2]]
//
// CHECK-BE-LABEL: @test_vcreateq_u32(
// CHECK-BE-NEXT: entry:
// CHECK-BE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
// CHECK-BE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[A:%.*]], i64 0
// CHECK-BE-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
// CHECK-BE-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vreinterpretq.v4i32.v2i64(<2 x i64> [[TMP1]])
// CHECK-BE-NEXT: ret <4 x i32> [[TMP2]]
Expand All @@ -154,7 +154,7 @@ uint32x4_t test_vcreateq_u32(uint64_t a, uint64_t b)

// CHECK-LABEL: @test_vcreateq_u64(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
// CHECK-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[A:%.*]], i64 0
// CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
// CHECK-NEXT: ret <2 x i64> [[TMP1]]
//
Expand All @@ -165,14 +165,14 @@ uint64x2_t test_vcreateq_u64(uint64_t a, uint64_t b)

// CHECK-LE-LABEL: @test_vcreateq_u8(
// CHECK-LE-NEXT: entry:
// CHECK-LE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
// CHECK-LE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[A:%.*]], i64 0
// CHECK-LE-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
// CHECK-LE-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to <16 x i8>
// CHECK-LE-NEXT: ret <16 x i8> [[TMP2]]
//
// CHECK-BE-LABEL: @test_vcreateq_u8(
// CHECK-BE-NEXT: entry:
// CHECK-BE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> undef, i64 [[A:%.*]], i64 0
// CHECK-BE-NEXT: [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[A:%.*]], i64 0
// CHECK-BE-NEXT: [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[B:%.*]], i64 1
// CHECK-BE-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vreinterpretq.v16i8.v2i64(<2 x i64> [[TMP1]])
// CHECK-BE-NEXT: ret <16 x i8> [[TMP2]]
Expand Down