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[SLP][REVEC] Ignore UserTreeIndex if it is empty. #131993

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Merged
HanKuanChen merged 4 commits into from
Mar 20, 2025
Merged

[SLP][REVEC] Ignore UserTreeIndex if it is empty. #131993

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e92f2ee
[SLP][REVEC] Pre-commit test.
HanKuanChen Mar 19, 2025
23ad559
[SLP][REVEC] Ignore UserTreeIndex if it is empty.
HanKuanChen Mar 19, 2025
bd6d98c
remove assert
HanKuanChen Mar 19, 2025
11dde44
apply comment
HanKuanChen Mar 19, 2025
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7 changes: 4 additions & 3 deletions llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -6449,9 +6449,10 @@ void BoUpSLP::reorderTopToBottom() {
assert(SLPReVec && "Only supported by REVEC.");
// ShuffleVectorInst does not do reorderOperands (and it should not
// because ShuffleVectorInst supports only a limited set of
// patterns). Only do reorderNodeWithReuses if all of the users are
// not ShuffleVectorInst.
if (isa<ShuffleVectorInst>(TE->UserTreeIndex.UserTE->getMainOp()))
// patterns). Only do reorderNodeWithReuses if the user is not
// ShuffleVectorInst.
if (TE->UserTreeIndex &&
isa<ShuffleVectorInst>(TE->UserTreeIndex.UserTE->getMainOp()))
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@alexey-bataev alexey-bataev Mar 19, 2025

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Some of the user may not have state, need to add a check for hasState() before asking for getMainOp

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@HanKuanChen HanKuanChen Mar 19, 2025

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How? If a TreeEntry has a user, that means the user must have MainOp inside InstructionsState. Otherwise, buildTree_rec cannot work.

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@alexey-bataev alexey-bataev Mar 19, 2025

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Some entries might have Gather parents

continue;
assert((!TE->UserTreeIndex ||
!isa<ShuffleVectorInst>(
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35 changes: 35 additions & 0 deletions llvm/test/Transforms/SLPVectorizer/X86/revec-reduced-value-replace-extractelement.ll
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@@ -0,0 +1,35 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -S --passes=slp-vectorizer -slp-threshold=-99999 < %s -mtriple=x86_64-unknown-linux-gnu -slp-revec | FileCheck %s

define void @test() {
; CHECK-LABEL: define void @test() {
; CHECK-NEXT: [[BB:.*]]:
; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 0 to i32
; CHECK-NEXT: br label %[[BB1:.*]]
; CHECK: [[BB1]]:
; CHECK-NEXT: [[TMP0:%.*]] = phi <2 x i32> [ zeroinitializer, %[[BB]] ], [ [[TMP4:%.*]], %[[BB1]] ]
; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[TMP0]], i32 1
; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.vector.reduce.mul.v4i8(<4 x i8> zeroinitializer)
; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32
; CHECK-NEXT: [[OP_RDX:%.*]] = mul i32 [[TMP3]], [[TMP1]]
; CHECK-NEXT: [[OP_RDX1:%.*]] = mul i32 [[OP_RDX]], [[TRUNC]]
; CHECK-NEXT: [[TMP4]] = insertelement <2 x i32> <i32 0, i32 poison>, i32 [[OP_RDX1]], i32 1
; CHECK-NEXT: br label %[[BB1]]
;
bb:
br label %bb1

bb1:
%phi = phi i32 [ 0, %bb ], [ %mul9, %bb1 ]
%phi2 = phi i32 [ 0, %bb ], [ 0, %bb1 ]
%trunc = trunc i64 0 to i32
%mul = mul i32 0, %trunc
%mul3 = mul i32 %trunc, %phi
%mul4 = mul i32 %mul3, %mul
%mul5 = mul i32 %mul4, %mul
%trunc6 = trunc i64 0 to i32
%mul7 = mul i32 0, %trunc6
%mul8 = mul i32 %mul5, %mul7
%mul9 = mul i32 %mul8, %mul7
br label %bb1
}