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[RISCV] Fix incorrect slide offset when using vnsrl to de-interleave #132123

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Merged
merged 3 commits into from
Mar 20, 2025
Merged

[RISCV] Fix incorrect slide offset when using vnsrl to de-interleave #132123

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d298e8c
[RISCV] Fix incorrect slide offset when using vnsrl to de-interleave
mshockwave Mar 19, 2025
1400fa9
fixup! Use INSERT_SUBVECTOR intead of using many CONCAT_VECTORS
mshockwave Mar 20, 2025
d1146cf
fixup! Address review comments
mshockwave Mar 20, 2025
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21 changes: 17 additions & 4 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5545,12 +5545,25 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
})) {
// Narrow each source and concatenate them.
// FIXME: For small LMUL it is better to concatenate first.
MVT HalfVT = VT.getHalfNumVectorElementsVT();
MVT EltVT = VT.getVectorElementType();
auto EltCnt = VT.getVectorElementCount();
MVT SubVT =
MVT::getVectorVT(EltVT, EltCnt.divideCoefficientBy(Factor));

SDValue Lo =
getDeinterleaveShiftAndTrunc(DL, HalfVT, V1, Factor, Index, DAG);
getDeinterleaveShiftAndTrunc(DL, SubVT, V1, Factor, Index, DAG);
SDValue Hi =
getDeinterleaveShiftAndTrunc(DL, HalfVT, V2, Factor, Index, DAG);
return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, Lo, Hi);
getDeinterleaveShiftAndTrunc(DL, SubVT, V2, Factor, Index, DAG);

MVT NewVT = SubVT.getDoubleNumVectorElementsVT();
SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, DL, NewVT, Lo, Hi);
for (unsigned F = Factor; F > 2; F >>= 1) {
SDValue Undef = DAG.getUNDEF(NewVT);
NewVT = NewVT.getDoubleNumVectorElementsVT();
Concat = DAG.getNode(ISD::CONCAT_VECTORS, DL, NewVT, Concat, Undef);
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@topperc topperc Mar 20, 2025

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Are we just slowly building an INSERT_SUBVECTOR?

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@mshockwave mshockwave Mar 20, 2025 •
edited
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Are we just slowly building an INSERT_SUBVECTOR?

The CONCAT_VECTORS lowering code does a similar thing on CONCAT_VECTORS with more than 2 operand which turns it into a tree of CONCAT_VECTORS. But I don't think this tree of CONCAT_VECTORS will become a single INSERT_SUBVECTOR.

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@topperc topperc Mar 20, 2025

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Can we use INSERT_SUBVECTOR here?

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@mshockwave mshockwave Mar 20, 2025

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Can we use INSERT_SUBVECTOR here?

Using INSERT_SUBVECTOR is indeed simpler. It's done know.

}

return Concat;
}
}
}
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6 changes: 4 additions & 2 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-deinterleave.ll
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Expand Up @@ -378,8 +378,9 @@ define void @deinterleave4_0_i8_two_source(ptr %in0, ptr %in1, ptr %out) {
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vnsrl.wi v9, v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v9, v8, 2
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v9, v8, 4
; CHECK-NEXT: vse8.v v9, (a2)
; CHECK-NEXT: ret
entry:
Expand All @@ -402,8 +403,9 @@ define void @deinterleave4_8_i8_two_source(ptr %in0, ptr %in1, ptr %out) {
; CHECK-NEXT: vsetvli zero, zero, e8, mf8, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: vnsrl.wi v9, v9, 0
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v9, v8, 2
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vslideup.vi v9, v8, 4
; CHECK-NEXT: vse8.v v9, (a2)
; CHECK-NEXT: ret
entry:
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