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[RISCV][VLOPT] Look through PHI instructions #132236

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Merged
michaelmaitland merged 7 commits into from
Mar 24, 2025
Merged

[RISCV][VLOPT] Look through PHI instructions #132236

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2513c59
[RISCV][VLOPT] Look through PHI instructions
michaelmaitland Mar 20, 2025
d6462da
fixup! clang-format
michaelmaitland Mar 20, 2025
25edefa
fixup! handle phi loop
michaelmaitland Mar 20, 2025
b1345f6
fixup! improve phi cycle logic
michaelmaitland Mar 20, 2025
b392433
fixup! add another test
michaelmaitland Mar 20, 2025
a268fed
fixup! remove accidental file
michaelmaitland Mar 20, 2025
c37a482
fixup! fix phi cycle logic
michaelmaitland Mar 24, 2025
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12 changes: 12 additions & 0 deletions llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1323,6 +1323,7 @@ std::optional<MachineOperand>
RISCVVLOptimizer::checkUsers(const MachineInstr &MI) const {
std::optional<MachineOperand> CommonVL;
SmallSetVector<MachineOperand *, 8> Worklist;
SmallPtrSet<const MachineInstr *, 4> PHISeen;
for (auto &UserOp : MRI->use_operands(MI.getOperand(0).getReg()))
Worklist.insert(&UserOp);

Expand All @@ -1340,6 +1341,17 @@ RISCVVLOptimizer::checkUsers(const MachineInstr &MI) const {
continue;
}

if (UserMI.isPHI() && PHISeen.insert(&UserMI).second) {
LLVM_DEBUG(dbgs() << " Peeking through uses of PHI\n");
for (auto &PhiUse : MRI->use_operands(UserMI.getOperand(0).getReg())) {
// If UserMI has a PHI cycle, don't analyze it.
if (PhiUse.getParent() == &UserMI)
continue;
Worklist.insert(&PhiUse);
}
continue;
}

auto VLOp = getMinimumVLForUser(UserOp);
if (!VLOp)
return std::nullopt;
Expand Down
108 changes: 108 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/vl-opt.mir
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Expand Up @@ -368,3 +368,111 @@ body: |
%y:vr = COPY %x
%z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */
...
---
name: phi
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: phi
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: BNE $noreg, $noreg, %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: %y:vr = PHI %w, %bb.0, %x, %bb.1
; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
bb.0:
%w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
BNE $noreg, $noreg, %bb.2
bb.1:
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
bb.2:
%y:vr = PHI %w, %bb.0, %x, %bb.1
%z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
...
---
name: phi_user_invalid_sew
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: phi_user_invalid_sew
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: BNE $noreg, $noreg, %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: %y:vr = PHI %w, %bb.0, %x, %bb.1
; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */
bb.0:
%w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
BNE $noreg, $noreg, %bb.2
bb.1:
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
bb.2:
%y:vr = PHI %w, %bb.0, %x, %bb.1
%z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 4 /* e16 */, 0 /* tu, mu */
...
---
name: phi_different_incoming_sew
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: phi_different_incoming_sew
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: BNE $noreg, $noreg, %bb.2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2:
; CHECK-NEXT: %y:vr = PHI %w, %bb.0, %x, %bb.1
; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
bb.0:
%w:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
BNE $noreg, $noreg, %bb.2
bb.1:
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
bb.2:
%y:vr = PHI %w, %bb.0, %x, %bb.1
%z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
...
---
name: phi_cycle
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: phi_cycle
; CHECK: bb.0:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %y:vr = PHI %x, %bb.0, %y, %bb.1
; CHECK-NEXT: %z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
; CHECK-NEXT: PseudoBR %bb.1
bb.0:
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 3 /* e8 */, 0 /* tu, mu */
bb.1:
%y:vr = PHI %x, %bb.0, %y, %bb.1
%z:vr = PseudoVADD_VV_M1 $noreg, %y, $noreg, 1, 3 /* e8 */, 0 /* tu, mu */
PseudoBR %bb.1
...

21 changes: 21 additions & 0 deletions patch.diff
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Original file line number Diff line number Diff line change
@@ -0,0 +1,21 @@
commit d6462da5dde7d38604bd5783e609ec8392eaf74c
Author: Michael Maitland <[email protected]>
Date: Thu Mar 20 08:21:12 2025 -0700

fixup! clang-format

diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 61f43e2e72b1..80ae0fd3d930 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -1342,8 +1342,8 @@ RISCVVLOptimizer::checkUsers(const MachineInstr &MI) const {

if (UserMI.isPHI()) {
LLVM_DEBUG(dbgs() << " Peeking through uses of PHI\n");
- for (auto &PhiUse : MRI->use_operands(UserMI.getOperand(0).getReg()))
- Worklist.insert(&PhiUse);
+ for (auto &PhiUse : MRI->use_operands(UserMI.getOperand(0).getReg()))
+ Worklist.insert(&PhiUse);
continue;
}

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