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[RISCV] Remove experimental from Sdext and Sdtrig which are ratified. #132529

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Merged
topperc merged 4 commits into from
Mar 24, 2025
Merged

[RISCV] Remove experimental from Sdext and Sdtrig which are ratified. #132529

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3b30343
[RISCV] Remove experimental from Sdext and Sdtrig which are ratified.
topperc Mar 22, 2025
c68251d
Merge remote-tracking branch 'origin/main' into pr/sdext-experimental
topperc Mar 24, 2025
8cefd3b
fixup! Update print-supported-extensions-riscv.c
topperc Mar 24, 2025
8a5f2ea
fixup! update features-info.ll
topperc Mar 24, 2025
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4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
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Original file line number Diff line number Diff line change
Expand Up @@ -869,9 +869,9 @@ def HasStdExtH : Predicate<"Subtarget->hasStdExtH()">,

// Supervisor extensions

def FeatureStdExtSdext : RISCVExperimentalExtension<1, 0, "External debugger">;
def FeatureStdExtSdext : RISCVExtension<1, 0, "External debugger">;

def FeatureStdExtSdtrig : RISCVExperimentalExtension<1, 0, "Debugger triggers">;
def FeatureStdExtSdtrig : RISCVExtension<1, 0, "Debugger triggers">;

def FeatureStdExtShgatpa
: RISCVExtension<1, 0,
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/attributes.ll
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Expand Up @@ -311,8 +311,8 @@
; RUN: llc -mtriple=riscv64 -mattr=+supm %s -o - | FileCheck --check-prefix=RV64SUPM %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smctr %s -o - | FileCheck --check-prefix=RV64SMCTR %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV64SSCTR %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-sdext %s -o - | FileCheck --check-prefix=RV64SDEXT %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s
; RUN: llc -mtriple=riscv64 -mattr=+sdext %s -o - | FileCheck --check-prefix=RV64SDEXT %s
; RUN: llc -mtriple=riscv64 -mattr=+sdtrig %s -o - | FileCheck --check-prefix=RV64SDTRIG %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-xqccmp %s -o - | FileCheck --check-prefix=RV64XQCCMP %s


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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/features-info.ll
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Expand Up @@ -15,8 +15,6 @@
; CHECK: e - 'E' (Embedded Instruction Set with 16 GPRs).
; CHECK: experimental - Experimental intrinsics.
; CHECK: experimental-rvm23u32 - RISC-V experimental-rvm23u32 profile.
; CHECK: experimental-sdext - 'Sdext' (External debugger).
; CHECK: experimental-sdtrig - 'Sdtrig' (Debugger triggers).
; CHECK: experimental-smctr - 'Smctr' (Control Transfer Records Machine Level).
; CHECK: experimental-ssctr - 'Ssctr' (Control Transfer Records Supervisor Level).
; CHECK: experimental-svukte - 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses).
Expand Down Expand Up @@ -96,6 +94,8 @@
; CHECK: rvi20u32 - RISC-V rvi20u32 profile.
; CHECK: rvi20u64 - RISC-V rvi20u64 profile.
; CHECK: save-restore - Enable save/restore..
; CHECK: sdext - 'Sdext' (External debugger).
; CHECK: sdtrig - 'Sdtrig' (Debugger triggers).
; CHECK: sha - 'Sha' (Augmented Hypervisor).
; CHECK: shcounterenw - 'Shcounterenw' (Support writeable hcounteren enable bit for any hpmcounter that is not read-only zero).
; CHECK: shgatpa - 'Shgatpa' (SvNNx4 mode supported for all modes supported by satp, as well as Bare).
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4 changes: 2 additions & 2 deletions llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
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Expand Up @@ -1058,6 +1058,8 @@ R"(All available -march extensions for RISC-V
zvl8192b 1.0
zhinx 1.0
zhinxmin 1.0
sdext 1.0
sdtrig 1.0
sha 1.0
shcounterenw 1.0
shgatpa 1.0
Expand Down Expand Up @@ -1137,8 +1139,6 @@ Experimental extensions
zvbc32e 0.7
zvkgs 0.7
zvqdotq 0.0
sdext 1.0
sdtrig 1.0
smctr 1.0
ssctr 1.0
svukte 0.3
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