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[MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs #132704

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Merged
merged 5 commits into from
Apr 29, 2025
Merged

[MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs #132704

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c5195f7
[MIPS] Add Scheduling model for MIPS i6400 and i6500 CPUs
mgoudar Mar 24, 2025
fc23bdf
Set MicroOpBufferSize and BufferSize to 0
mgoudar Mar 26, 2025
6784668
Address review comments
mgoudar Mar 27, 2025
59e72f4
Cover more instructions in llvm-mca test
mgoudar Apr 4, 2025
bb2188a
Update llvm-mca test and rerun update_mca_test_checks.py
mgoudar Apr 9, 2025
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5 changes: 3 additions & 2 deletions llvm/lib/Target/Mips/Mips.td
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Original file line number Diff line number Diff line change
Expand Up @@ -224,6 +224,7 @@ include "MipsRegisterBanks.td"
include "MipsCombine.td"

// Avoid forward declaration issues.
include "MipsScheduleI6400.td"
include "MipsScheduleP5600.td"
include "MipsScheduleGeneric.td"

Expand Down Expand Up @@ -271,8 +272,8 @@ def : Proc<"mips64r6", [FeatureMips64r6]>;
def : Proc<"octeon", [FeatureMips64r2, FeatureCnMips]>;
def : Proc<"octeon+", [FeatureMips64r2, FeatureCnMips, FeatureCnMipsP]>;
def : ProcessorModel<"p5600", MipsP5600Model, [ImplP5600]>;
def : ProcessorModel<"i6400", NoSchedModel, [ImplI6400]>;
def : ProcessorModel<"i6500", NoSchedModel, [ImplI6500]>;
def : ProcessorModel<"i6400", MipsI6400Model, [ImplI6400]>;
def : ProcessorModel<"i6500", MipsI6400Model, [ImplI6500]>;

def MipsAsmParser : AsmParser {
let ShouldEmitMatchRegisterName = 0;
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