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9 changes: 4 additions & 5 deletions llvm/utils/TableGen/Common/CodeGenRegisters.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2103,9 +2103,7 @@ void CodeGenRegBank::computeRegUnitSets() {

// For each register class, list the UnitSets that are supersets.
RegClassUnitSets.resize(RegClasses.size());
int RCIdx = -1;
for (auto &RC : RegClasses) {
++RCIdx;
if (!RC.Allocatable)
continue;

Expand All @@ -2127,12 +2125,13 @@ void CodeGenRegBank::computeRegUnitSets() {
++USIdx) {
if (isRegUnitSubSet(RCRegUnits, RegUnitSets[USIdx].Units)) {
LLVM_DEBUG(dbgs() << " " << USIdx);
RegClassUnitSets[RCIdx].push_back(USIdx);
RegClassUnitSets[RC.EnumValue].push_back(USIdx);
}
}
LLVM_DEBUG(dbgs() << "\n");
assert((!RegClassUnitSets[RCIdx].empty() || !RC.GeneratePressureSet) &&
"missing unit set for regclass");
assert(
(!RegClassUnitSets[RC.EnumValue].empty() || !RC.GeneratePressureSet) &&
"missing unit set for regclass");
}

// For each register unit, ensure that we have the list of UnitSets that
Expand Down