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[RISCV] Use named sub-operands to simplify encoding/decoding for CoreV Reg-Reg instructions. #133181

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Merged
merged 2 commits into from
Mar 27, 2025
Merged

[RISCV] Use named sub-operands to simplify encoding/decoding for CoreV Reg-Reg instructions. #133181

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95c94cb
[RISCV] Use named sub-operands to simplify encoding/decoding for Core…
topperc Mar 26, 2025
d1bad99
fixup! rename the operand to $addr.
topperc Mar 26, 2025
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12 changes: 0 additions & 12 deletions llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -507,9 +507,6 @@ static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm,
uint64_t Address, const void *Decoder);

static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address,
const MCDisassembler *Decoder);

static DecodeStatus decodeZcmpSpimm(MCInst &Inst, uint32_t Imm,
uint64_t Address, const void *Decoder);

Expand Down Expand Up @@ -621,15 +618,6 @@ static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm,
return MCDisassembler::Success;
}

static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address,
const MCDisassembler *Decoder) {
uint32_t Rs1 = fieldFromInstruction(Insn, 0, 5);
uint32_t Rs2 = fieldFromInstruction(Insn, 5, 5);
DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder);
DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
return MCDisassembler::Success;
}

static DecodeStatus decodeZcmpSpimm(MCInst &Inst, uint32_t Imm,
uint64_t Address, const void *Decoder) {
Inst.addOperand(MCOperand::createImm(Imm));
Expand Down
17 changes: 0 additions & 17 deletions llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
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Expand Up @@ -103,10 +103,6 @@ class RISCVMCCodeEmitter : public MCCodeEmitter {
unsigned getRlistOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;

unsigned getRegReg(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
};
} // end anonymous namespace

Expand Down Expand Up @@ -621,17 +617,4 @@ unsigned RISCVMCCodeEmitter::getRlistOpValue(const MCInst &MI, unsigned OpNo,
return Imm;
}

unsigned RISCVMCCodeEmitter::getRegReg(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const {
const MCOperand &MO = MI.getOperand(OpNo);
const MCOperand &MO1 = MI.getOperand(OpNo + 1);
assert(MO.isReg() && MO1.isReg() && "Expected registers.");

unsigned Op = Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
unsigned Op1 = Ctx.getRegisterInfo()->getEncodingValue(MO1.getReg());

return Op | Op1 << 5;
}

#include "RISCVGenMCCodeEmitter.inc"
29 changes: 10 additions & 19 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
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Expand Up @@ -24,10 +24,8 @@ def CVrrAsmOperand : AsmOperandClass {
def CVrr : Operand<i32>,
ComplexPattern<i32, 2, "SelectAddrRegReg",[]> {
let ParserMatchClass = CVrrAsmOperand;
let EncoderMethod = "getRegReg";
let DecoderMethod = "decodeRegReg";
let PrintMethod = "printRegReg";
let MIOperandInfo = (ops GPR:$base, GPR:$offset);
let MIOperandInfo = (ops GPR:$offset, GPR:$base);
}

def cv_tuimm2 : TImmLeaf<XLenVT, [{return isUInt<2>(Imm);}]>;
Expand Down Expand Up @@ -288,17 +286,9 @@ class CVLoad_rr_inc<bits<7> funct7, bits<3> funct3, string opcodestr>
}

class CVLoad_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
: RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd), (ins CVrr:$cvrr),
opcodestr, "$rd, $cvrr"> {
bits<5> rd;
bits<10> cvrr;

let Inst{31-25} = funct7;
let Inst{24-20} = cvrr{4-0};
let Inst{19-15} = cvrr{9-5};
let Inst{14-12} = funct3;
let Inst{11-7} = rd;
}
: RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd),
(ins (CVrr $rs2, $rs1):$addr),
opcodestr, "$rd, $addr">;
} // hasSideEffects = 0, mayLoad = 1, mayStore = 0

let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
Expand Down Expand Up @@ -327,16 +317,17 @@ class CVStore_rr_inc<bits<3> funct3, bits<7> funct7, string opcodestr>


class CVStore_rr<bits<3> funct3, bits<7> funct7, string opcodestr>
: RVInst<(outs), (ins GPR:$rs2, CVrr:$cvrr), opcodestr, "$rs2, $cvrr", [],
InstFormatOther> {
: RVInst<(outs), (ins GPR:$rs2, (CVrr $rs3, $rs1):$addr), opcodestr,
"$rs2, $addr", [], InstFormatOther> {
bits<5> rs1;
bits<5> rs2;
bits<10> cvrr;
bits<5> rs3;

let Inst{31-25} = funct7;
let Inst{24-20} = rs2;
let Inst{19-15} = cvrr{9-5};
let Inst{19-15} = rs1;
let Inst{14-12} = funct3;
let Inst{11-7} = cvrr{4-0};
let Inst{11-7} = rs3;
let Inst{6-0} = OPC_CUSTOM_1.Value;
}
} // hasSideEffects = 0, mayLoad = 0, mayStore = 1
Expand Down