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RISCVAsmParser: Don't treat operands with relocation specifier as parse-time constants #133377

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Merged
merged 6 commits into from
Mar 29, 2025
Merged

RISCVAsmParser: Don't treat operands with relocation specifier as parse-time constants #133377

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028d669
[𝘀𝗽𝗿] initial version
MaskRay Mar 28, 2025
037e7fd
.
MaskRay Mar 28, 2025
35830c2
rebase. update all tests
MaskRay Mar 28, 2025
4aa5e9b
Simplify simm12 and uimm20 (lui,auipc)
MaskRay Mar 28, 2025
29b2fbd
delete unneeded IsValid
MaskRay Mar 28, 2025
883671e
rebase
MaskRay Mar 29, 2025
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247 changes: 87 additions & 160 deletions llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
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27 changes: 0 additions & 27 deletions llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -164,30 +164,3 @@ StringRef RISCVMCExpr::getSpecifierName(Specifier S) {
}
llvm_unreachable("Invalid ELF symbol kind");
}

bool RISCVMCExpr::evaluateAsConstant(int64_t &Res) const {
MCValue Value;
if (specifier != VK_LO && specifier != VK_HI)
return false;

if (!getSubExpr()->evaluateAsRelocatable(Value, nullptr))
return false;

if (!Value.isAbsolute())
return false;

Res = evaluateAsInt64(Value.getConstant());
return true;
}

int64_t RISCVMCExpr::evaluateAsInt64(int64_t Value) const {
switch (specifier) {
default:
llvm_unreachable("Invalid kind");
case VK_LO:
return SignExtend64<12>(Value);
case VK_HI:
// Add 1 if bit 11 is 1, to compensate for low 12 bits being negative.
return ((Value + 0x800) >> 12) & 0xfffff;
}
}
8 changes: 4 additions & 4 deletions llvm/test/MC/RISCV/insn.s
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Expand Up @@ -146,12 +146,12 @@ target:
# CHECK-OBJ: fmadd.s fa0, fa1, fa2, fa3, rne
.insn r4 MADD, 0, 0, fa0, fa1, fa2, fa3

# CHECK-ASM: .insn i 3, 5, t1, -2048(t2)
# CHECK-ASM: encoding: [0x03,0xd3,0x03,0x80]
# CHECK-ASM: .insn i 3, 5, t1, %lo(2048)(t2)
# CHECK-ASM: encoding: [0x03,0xd3,0bAAAA0011,A]
# CHECK-OBJ: lhu t1, -0x800(t2)
.insn i 0x3, 0x5, x6, %lo(2048)(x7)
# CHECK-ASM: .insn i 3, 5, t1, -2048(t2)
# CHECK-ASM: encoding: [0x03,0xd3,0x03,0x80]
# CHECK-ASM: .insn i 3, 5, t1, %lo(2048)(t2)
# CHECK-ASM: encoding: [0x03,0xd3,0bAAAA0011,A]
# CHECK-OBJ: lhu t1, -0x800(t2)
.insn i LOAD, 0x5, x6, %lo(2048)(x7)

Expand Down
5 changes: 3 additions & 2 deletions llvm/test/MC/RISCV/rv32i-aliases-valid.s
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Expand Up @@ -83,8 +83,9 @@ li x12, 0x80000000
# CHECK-ALIAS: li a2, -1
li x12, 0xFFFFFFFF

# CHECK-INST: addi a0, zero, 1110
# CHECK-ALIAS: li a0, 1110
# CHECK-ASM-NOALIAS: addi a0, zero, %lo(1193046)
# CHECK-OBJ-NOALIAS: addi a0, zero, 1110
# CHECK-ASM: addi a0, zero, %lo(1193046)
li a0, %lo(0x123456)

# CHECK-OBJ-NOALIAS: addi a0, zero, 0
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/MC/RISCV/rvd-valid.s
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Expand Up @@ -23,8 +23,8 @@ fld f1, +4(ra)
# CHECK-ASM-AND-OBJ: fld ft2, -2048(a3)
# CHECK-ASM: encoding: [0x07,0xb1,0x06,0x80]
fld f2, -2048(x13)
# CHECK-ASM-AND-OBJ: fld ft3, -2048(s1)
# CHECK-ASM: encoding: [0x87,0xb1,0x04,0x80]
# CHECK-ASM: fld ft3, %lo(2048)(s1) # encoding: [0x87,0xb1,0bAAAA0100,A]
# CHECK-OBJ: fld ft3, -2048(s1)
fld f3, %lo(2048)(s1)
# CHECK-ASM-AND-OBJ: fld ft4, 2047(s2)
# CHECK-ASM: encoding: [0x07,0x32,0xf9,0x7f]
Expand All @@ -39,8 +39,8 @@ fsd f6, 2047(s4)
# CHECK-ASM-AND-OBJ: fsd ft7, -2048(s5)
# CHECK-ASM: encoding: [0x27,0xb0,0x7a,0x80]
fsd f7, -2048(s5)
# CHECK-ASM-AND-OBJ: fsd fs0, -2048(s6)
# CHECK-ASM: encoding: [0x27,0x30,0x8b,0x80]
# CHECK-ASM: fsd fs0, %lo(2048)(s6) # encoding: [0x27'A',0x30'A',0x8b'A',A]
# CHECK-OBJ: fsd fs0, -2048(s6)
fsd f8, %lo(2048)(s6)
# CHECK-ASM-AND-OBJ: fsd fs1, 999(s7)
# CHECK-ASM: encoding: [0xa7,0xb3,0x9b,0x3e]
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/MC/RISCV/rvf-valid.s
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Expand Up @@ -18,8 +18,8 @@ flw f1, +4(ra)
# CHECK-ASM-AND-OBJ: flw ft2, -2048(a3)
# CHECK-ASM: encoding: [0x07,0xa1,0x06,0x80]
flw f2, -2048(x13)
# CHECK-ASM-AND-OBJ: flw ft3, -2048(s1)
# CHECK-ASM: encoding: [0x87,0xa1,0x04,0x80]
# CHECK-ASM: flw ft0, %lo(2048)(s6) # encoding: [0x27'A',0x20'A',0x8b'A',A]
# CHECK-OBJ: flw ft3, -2048(s1)
flw f3, %lo(2048)(s1)
# CHECK-ASM-AND-OBJ: flw ft4, 2047(s2)
# CHECK-ASM: encoding: [0x07,0x22,0xf9,0x7f]
Expand Down
28 changes: 16 additions & 12 deletions llvm/test/MC/RISCV/rvi-valid.s
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Expand Up @@ -20,14 +20,15 @@ lui a0, 2
# CHECK-ASM-AND-OBJ: lui s11, 552960
# CHECK-ASM: encoding: [0xb7,0x0d,0x00,0x87]
lui s11, (0x87000000>>12)
# CHECK-ASM-AND-OBJ: lui a0, 0
# CHECK-ASM: encoding: [0x37,0x05,0x00,0x00]
# CHECK-ASM: lui a0, %hi(2) # encoding: [0x37,0bAAAA0101,A,A]
# CHECK-OBJ: lui a0, 0
lui a0, %hi(2)
# CHECK-ASM-AND-OBJ: lui s11, 552960
# CHECK-ASM: encoding: [0xb7,0x0d,0x00,0x87]
lui s11, (0x87000000>>12)
# CHECK-ASM-AND-OBJ: lui s11, 552960
# CHECK-ASM: encoding: [0xb7,0x0d,0x00,0x87]
# CHECK-ASM: lui s11, %hi(2264924160)
# CHECK-OBJ: lui s11, 552960
# CHECK-ASM: encoding: [0xb7,0bAAAA1101,A,A]
lui s11, %hi(0x87000000)
# CHECK-ASM-AND-OBJ: lui t0, 1048575
# CHECK-ASM: encoding: [0xb7,0xf2,0xff,0xff]
Expand Down Expand Up @@ -104,8 +105,9 @@ jal zero, .
# CHECK-ASM-AND-OBJ: jalr a0, -2048(a1)
# CHECK-ASM: encoding: [0x67,0x85,0x05,0x80]
jalr a0, -2048(a1)
# CHECK-ASM-AND-OBJ: jalr a0, -2048(a1)
# CHECK-ASM: encoding: [0x67,0x85,0x05,0x80]
# CHECK-ASM: jalr a0, %lo(2048)(a1)
# CHECK-ASM: encoding: [0x67,0x85,0bAAAA0101,A]
# CHECK-OBJ: jalr a0, -2048(a1)
jalr a0, %lo(2048)(a1)
# CHECK-ASM-AND-OBJ: jalr t2, 2047(t1)
# CHECK-ASM: encoding: [0xe7,0x03,0xf3,0x7f]
Expand Down Expand Up @@ -162,8 +164,9 @@ lh t1, ~2047(zero)
# CHECK-ASM-AND-OBJ: lh t1, 0(zero)
# CHECK-ASM: encoding: [0x03,0x13,0x00,0x00]
lh t1, !1(zero)
# CHECK-ASM-AND-OBJ: lh t1, -2048(zero)
# CHECK-ASM: encoding: [0x03,0x13,0x00,0x80]
# CHECK-ASM: lh t1, %lo(2048)(zero)
# CHECK-ASM: encoding: [0x03,0x13,0bAAAA0000,A]
# CHECK-OBJ: lh t1, -2048(zero)
lh t1, %lo(2048)(zero)
# CHECK-ASM-AND-OBJ: lh sp, 2047(a0)
# CHECK-ASM: encoding: [0x03,0x11,0xf5,0x7f]
Expand Down Expand Up @@ -203,8 +206,9 @@ sh t3, ~2047(t5)
# CHECK-ASM-AND-OBJ: sh t3, 0(t5)
# CHECK-ASM: encoding: [0x23,0x10,0xcf,0x01]
sh t3, !1(t5)
# CHECK-ASM-AND-OBJ: sh t3, -2048(t5)
# CHECK-ASM: encoding: [0x23,0x10,0xcf,0x81]
# CHECK-ASM: sh t3, %lo(2048)(t5)
# CHECK-ASM: encoding: [0x23'A',0x10'A',0xcf'A',0x01'A']
# CHECK-OBJ: sh t3, -2048(t5)
sh t3, %lo(2048)(t5)
# CHECK-ASM-AND-OBJ: sw ra, 999(zero)
# CHECK-ASM: encoding: [0xa3,0x23,0x10,0x3e]
Expand Down Expand Up @@ -254,8 +258,8 @@ ori a0, a1, ~2047
# CHECK-ASM-AND-OBJ: ori a0, a1, 0
# CHECK-ASM: encoding: [0x13,0xe5,0x05,0x00]
ori a0, a1, !1
# CHECK-ASM-AND-OBJ: ori a0, a1, -2048
# CHECK-ASM: encoding: [0x13,0xe5,0x05,0x80]
# CHECK-ASM: ori a0, a1, %lo(2048) # encoding: [0x13,0xe5,0bAAAA0101,A]
# CHECK-OBJ: ori a0, a1, -2048
ori a0, a1, %lo(2048)
# CHECK-ASM-AND-OBJ: andi ra, sp, 2047
# CHECK-ASM: encoding: [0x93,0x70,0xf1,0x7f]
Expand Down
5 changes: 3 additions & 2 deletions llvm/test/MC/RISCV/rvzfh-valid.s
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Expand Up @@ -18,8 +18,9 @@ flh f1, +4(ra)
# CHECK-ASM-AND-OBJ: flh ft2, -2048(a3)
# CHECK-ASM: encoding: [0x07,0x91,0x06,0x80]
flh f2, -2048(x13)
# CHECK-ASM-AND-OBJ: flh ft3, -2048(s1)
# CHECK-ASM: encoding: [0x87,0x91,0x04,0x80]
# CHECK-ASM: flh ft3, %lo(2048)(s1)
# CHECCK-ASM: encoding: [0x87,0x91,0xAAAA0100,A]
# CHECK-OBJ: flh ft3, -2048(s1)
flh f3, %lo(2048)(s1)
# CHECK-ASM-AND-OBJ: flh ft4, 2047(s2)
# CHECK-ASM: encoding: [0x07,0x12,0xf9,0x7f]
Expand Down
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