Skip to content

[AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies inserted by PHI preprocessing. #134153

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
alex-t merged 9 commits into from
Apr 10, 2025
Merged

[AMDGPU] SIFixSgprCopies should not process twice VGPR to SGPR copies inserted by PHI preprocessing. #134153

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
9 commits
Select commit Hold shift + click to select a range
042c955
[AMDGPU] SIFixSGPRCopies should not process twice V2S copies created…
alex-t Apr 2, 2025
4dbb98d
Update llvm/test/CodeGen/AMDGPU/triton_regression_no_waterfall.ll
alex-t Apr 10, 2025
74c6a35
Update llvm/test/CodeGen/AMDGPU/triton_regression_no_waterfall.ll
alex-t Apr 10, 2025
6c4287d
Update llvm/test/CodeGen/AMDGPU/triton_regression_no_waterfall.ll
alex-t Apr 10, 2025
3838c8d
Update llvm/test/CodeGen/AMDGPU/triton_regression_no_waterfall.mir
alex-t Apr 10, 2025
378ad53
Update llvm/test/CodeGen/AMDGPU/triton_regression_no_waterfall.mir
alex-t Apr 10, 2025
69f2f1e
Update llvm/test/CodeGen/AMDGPU/triton_regression_no_waterfall.mir
alex-t Apr 10, 2025
017b198
Update llvm/test/CodeGen/AMDGPU/triton_regression_no_waterfall.mir
alex-t Apr 10, 2025
dcbcd14
Update llvm/test/CodeGen/AMDGPU/triton_regression_no_waterfall.mir
alex-t Apr 10, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
14 changes: 8 additions & 6 deletions llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -127,6 +127,7 @@ class SIFixSGPRCopies {
unsigned NextVGPRToSGPRCopyID = 0;
MapVector<unsigned, V2SCopyInfo> V2SCopies;
DenseMap<MachineInstr *, SetVector<unsigned>> SiblingPenalty;
DenseSet<MachineInstr *> PHISources;

public:
MachineRegisterInfo *MRI;
Expand Down Expand Up @@ -691,10 +692,8 @@ bool SIFixSGPRCopies::run(MachineFunction &MF) {
TII->get(AMDGPU::COPY), NewDst)
.addReg(MO.getReg());
MO.setReg(NewDst);

// FIXME: We are transitively revisiting users of this
// instruction for every input.
analyzeVGPRToSGPRCopy(NewCopy);
PHISources.insert(NewCopy);
}
}
}
Expand Down Expand Up @@ -801,6 +800,7 @@ bool SIFixSGPRCopies::run(MachineFunction &MF) {
RegSequences.clear();
PHINodes.clear();
S2VCopies.clear();
PHISources.clear();

return true;
}
Expand Down Expand Up @@ -926,13 +926,13 @@ bool SIFixSGPRCopies::lowerSpecialCase(MachineInstr &MI,
}

void SIFixSGPRCopies::analyzeVGPRToSGPRCopy(MachineInstr* MI) {
if (PHISources.contains(MI))
return;
Register DstReg = MI->getOperand(0).getReg();
const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);

V2SCopyInfo Info(getNextVGPRToSGPRCopyId(), MI,
TRI->getRegSizeInBits(*DstRC));
V2SCopies[Info.ID] = Info;

SmallVector<MachineInstr *, 8> AnalysisWorklist;
// Needed because the SSA is not a tree but a graph and may have
// forks and joins. We should not then go same way twice.
Expand Down Expand Up @@ -971,16 +971,18 @@ void SIFixSGPRCopies::analyzeVGPRToSGPRCopy(MachineInstr* MI) {
}
} else if (Inst->getNumExplicitDefs() != 0) {
Register Reg = Inst->getOperand(0).getReg();
if (TRI->isSGPRReg(*MRI, Reg) && !TII->isVALU(*Inst))
if (Reg.isVirtual() && TRI->isSGPRReg(*MRI, Reg) && !TII->isVALU(*Inst)) {
for (auto &U : MRI->use_instructions(Reg))
Users.push_back(&U);
}
}
for (auto *U : Users) {
if (TII->isSALU(*U))
Info.SChain.insert(U);
AnalysisWorklist.push_back(U);
}
}
V2SCopies[Info.ID] = Info;
}

// The main function that computes the VGPR to SGPR copy score
Expand Down
Loading
Loading