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[RISCV] Don't allow mixing ABI and non-ABI register names when parsing register list. #134210

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[RISCV] Don't allow mixing ABI and non-ABI register names when parsing register list. #134210

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24 changes: 19 additions & 5 deletions llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2587,6 +2587,7 @@ ParseStatus RISCVAsmParser::parseRegListCommon(OperandVector &Operands,
return Error(getLoc(), "register list must start from 'ra' or 'x1'");

StringRef RegName = getLexer().getTok().getIdentifier();
bool XRegs = RegName[0] == 'x';
MCRegister RegEnd = matchRegisterNameHelper(RegName);
if (RegEnd != RISCV::X1)
return Error(getLoc(), "register list must start from 'ra' or 'x1'");
Expand All @@ -2597,6 +2598,9 @@ ParseStatus RISCVAsmParser::parseRegListCommon(OperandVector &Operands,
if (getLexer().isNot(AsmToken::Identifier))
return Error(getLoc(), "invalid register");
StringRef RegName = getLexer().getTok().getIdentifier();
// If 'x1' was used intead of 'ra', this must be 'x8' and not 's0'.
if (XRegs != (RegName[0] == 'x'))
return Error(getLoc(), "invalid register");
RegEnd = matchRegisterNameHelper(RegName);
if (!RegEnd)
return Error(getLoc(), "invalid register");
Expand All @@ -2608,10 +2612,14 @@ ParseStatus RISCVAsmParser::parseRegListCommon(OperandVector &Operands,
// parse case like -s1
if (parseOptionalToken(AsmToken::Minus)) {
StringRef EndName = getLexer().getTok().getIdentifier();
// FIXME: the register mapping and checks of RVE is wrong
// If 'x1' and 'x8' were used, this must also start with 'x'.
if (XRegs != (EndName[0] == 'x'))
return Error(getLoc(), "invalid register");
RegEnd = matchRegisterNameHelper(EndName);
// If 'x8' was used instead of 's0', this must be 'x9' and can't be
// 'x18'-'x27'.
if (!(RegEnd == RISCV::X9 ||
(RegEnd >= RISCV::X18 && RegEnd <= RISCV::X27)))
(!XRegs && RegEnd >= RISCV::X18 && RegEnd <= RISCV::X27)))
return Error(getLoc(), "invalid register");
getLexer().Lex();
}
Expand All @@ -2624,10 +2632,13 @@ ParseStatus RISCVAsmParser::parseRegListCommon(OperandVector &Operands,
"first contiguous registers pair of register list must be 'x8-x9'");

// parse ', x18' for extra part
if (getLexer().isNot(AsmToken::Identifier) || IsRVE)
if (getLexer().isNot(AsmToken::Identifier) || IsRVE || !XRegs)
return Error(getLoc(), "invalid register");
StringRef EndName = getLexer().getTok().getIdentifier();
RegEnd = MatchRegisterName(EndName);
// If 'x1' and 'x8' were used, this must also start with 'x'.
if (EndName[0] != 'x')
return Error(getLoc(), "invalid register");
RegEnd = matchRegisterNameHelper(EndName);
if (RegEnd != RISCV::X18)
return Error(getLoc(),
"second contiguous registers pair of register list "
Expand All @@ -2639,7 +2650,10 @@ ParseStatus RISCVAsmParser::parseRegListCommon(OperandVector &Operands,
if (getLexer().isNot(AsmToken::Identifier) || IsRVE)
return Error(getLoc(), "invalid register");
EndName = getLexer().getTok().getIdentifier();
RegEnd = MatchRegisterName(EndName);
// If 'x1' and 'x8' were used, this must also start with 'x'.
if (EndName[0] != 'x')
return Error(getLoc(), "invalid register");
RegEnd = matchRegisterNameHelper(EndName);
if (!(RegEnd >= RISCV::X19 && RegEnd <= RISCV::X27))
return Error(getLoc(), "invalid register");
getLexer().Lex();
Expand Down
11 changes: 7 additions & 4 deletions llvm/test/MC/RISCV/rv32zcmp-invalid.s
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Original file line number Diff line number Diff line change
Expand Up @@ -35,13 +35,16 @@ cm.pop {ra, t1}, -40
cm.pop {ra, s0-t1}, -40

# CHECK-ERROR: :[[@LINE+1]]:20: error: second contiguous registers pair of register list must start from 'x18'
cm.pop {ra, x8-x9, x28}, -40
cm.pop {x1, x8-x9, x28}, -40

# CHECK-ERROR: :[[@LINE+1]]:24: error: invalid register
cm.pop {ra, x8-x9, x18-x28}, -40
cm.pop {x1, x8-x9, x18-x28}, -40

# CHECK-ERROR: :[[@LINE+1]]:24: error: invalid register
cm.pop {ra, x8-x9, x18-x17}, -40
cm.pop {x1, x8-x9, x18-x17}, -40

# CHECK-ERROR: :[[@LINE+1]]:16: error: invalid register
cm.pop {ra, x8-f8, x18-x17}, -40
cm.pop {x1, x8-f8, x18-x17}, -40

# CHECK-ERROR: :[[@LINE+1]]:16: error: invalid register
cm.pop {ra, s0-f8}, -40
35 changes: 31 additions & 4 deletions llvm/test/MC/RISCV/rv64zcmp-invalid.s
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Original file line number Diff line number Diff line change
Expand Up @@ -38,16 +38,16 @@ cm.pop {ra, t1}, -40
cm.pop {ra, s0-t1}, -40

# CHECK-ERROR: :[[@LINE+1]]:20: error: second contiguous registers pair of register list must start from 'x18'
cm.pop {ra, x8-x9, x28}, -40
cm.pop {x1, x8-x9, x28}, -40

# CHECK-ERROR: :[[@LINE+1]]:24: error: invalid register
cm.pop {ra, x8-x9, x18-x28}, -40
cm.pop {x1, x8-x9, x18-x28}, -40

# CHECK-ERROR: :[[@LINE+1]]:24: error: invalid register
cm.pop {ra, x8-x9, x18-x17}, -40
cm.pop {x1, x8-x9, x18-x17}, -40

# CHECK-ERROR: :[[@LINE+1]]:16: error: invalid register
cm.pop {ra, x8-f8, x18-x17}, -40
cm.pop {x1, x8-f8, x18-x17}, -40

# CHECK-ERROR: :[[@LINE+1]]:15: error: stack adjustment is invalid for this instruction and register list
cm.pop {ra}, -x1
Expand All @@ -57,3 +57,30 @@ cm.push {ra}, x1

# CHECK-ERROR: :[[@LINE+1]]:12: error: register list must end with '}'
cm.push {x1-x9}, -32

# CHECK-ERROR: :[[@LINE+1]]:13: error: invalid register
cm.push {x1,s0}

# CHECK-ERROR: :[[@LINE+1]]:13: error: invalid register
cm.push {ra,x8}

# CHECK-ERROR: :[[@LINE+1]]:16: error: invalid register
cm.push {x1,x8-s1}

# CHECK-ERROR: :[[@LINE+1]]:16: error: invalid register
cm.push {ra,s0-x9}

# CHECK-ERROR: :[[@LINE+1]]:16: error: invalid register
cm.push {x1,x8-x18}

# CHECK-ERROR: :[[@LINE+1]]:19: error: invalid register
cm.push {x1,x8-x9,s2}

# CHECK-ERROR: :[[@LINE+1]]:19: error: invalid register
cm.push {ra,s0-s1,x18}

# CHECK-ERROR: :[[@LINE+1]]:19: error: invalid register
cm.push {ra,s0-s1,s2}

# CHECK-ERROR: :[[@LINE+1]]:23: error: invalid register
cm.push {x1,x8-x9,x18-s3}
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