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[MIPS] Add FeatureMSA to i6400 and i6500 cores #134985

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Merged
merged 8 commits into from
May 7, 2025
Merged

[MIPS] Add FeatureMSA to i6400 and i6500 cores #134985

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36a78bb
[MIPS] Add FeatureMSA to i6400 and i6500 cores
mgoudar Apr 1, 2025
4ed92eb
Update test case with update_llc_test_checks.py
mgoudar Apr 10, 2025
8f2d850
Add test case to test MSA feature for i6400 and i6500 MIPS cpus
mgoudar Apr 17, 2025
f1b35e8
Enable MSA feature by default for MIPS cpus i6400 and i6500
mgoudar Apr 23, 2025
dad1337
Revert "Enable MSA feature by default for MIPS cpus i6400 and i6500"
mgoudar Apr 23, 2025
53467c3
Revert "Revert "Enable MSA feature by default for MIPS cpus i6400 and…
mgoudar Apr 23, 2025
9a1e1ea
add llvm codegen test to validate MSA instructions for CPU i6500 and …
mgoudar Apr 23, 2025
79fd97c
Use llvm/test/CodeGen/Mips/msa/arithmetic.ll for i6500 test
mgoudar May 6, 2025
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4 changes: 2 additions & 2 deletions llvm/lib/Target/Mips/Mips.td
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Original file line number Diff line number Diff line change
Expand Up @@ -242,11 +242,11 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl",
// same CPU architecture.
def ImplI6400
: SubtargetFeature<"i6400", "ProcImpl", "MipsSubtarget::CPU::I6400",
"MIPS I6400 Processor", [FeatureMips64r6]>;
"MIPS I6400 Processor", [FeatureMips64r6, FeatureMSA]>;

def ImplI6500
: SubtargetFeature<"i6500", "ProcImpl", "MipsSubtarget::CPU::I6500",
"MIPS I6500 Processor", [FeatureMips64r6]>;
"MIPS I6500 Processor", [FeatureMips64r6, FeatureMSA]>;

class Proc<string Name, list<SubtargetFeature> Features>
: ProcessorModel<Name, MipsGenericModel, Features>;
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69 changes: 69 additions & 0 deletions llvm/test/CodeGen/Mips/msa/i6500.ll
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@@ -0,0 +1,69 @@
; Test the MSA intrinsics that are encoded with the SPECIAL instruction format.
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@mshockwave mshockwave Apr 9, 2025

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Could we use update_llc_test_checks.py to maintain this test?

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@mgoudar mgoudar Apr 17, 2025 •
edited
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I have written driver test mips-cpus.c instead of codegen as you suggested.
as mips-cpus.c test, we need to enable MSA feature via -mmsa flag. I think we need to enable this as part of i6500 cpu flag by default via driver. please suggest.

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@mgoudar mgoudar Apr 23, 2025

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I have enabled MSA feature from driver also when -mcpu i6500/i6400 is specified. Also I have added codegen test to verify MSA instructions when i650/i6400 cpu is specified. please review


; RUN: llc -mtriple=mips-elf -mcpu=i6500 < %s | \
; RUN: FileCheck %s --check-prefix=MIPS32
; RUN: llc -mtriple=mips64-elf -mcpu=i6500 < %s | \
; RUN: FileCheck %s --check-prefix=MIPS64
; RUN: llc -mtriple=mips-elf -mcpu=i6500 < %s | \
; RUN: FileCheck %s --check-prefix=MIPS32
; RUN: llc -mtriple=mips64-elf -mcpu=i6500 < %s | \
; RUN: FileCheck %s --check-prefix=MIPS64
; RUN: llc -mtriple=mips64-elf -mcpu=i6500 -mattr=-msa < %s | \
; RUN: FileCheck %s --check-prefix=NO-DSLA
; RUN: llc -mtriple=mips-elf -mcpu=i6400 < %s | \
; RUN: FileCheck %s --check-prefix=MIPS32
; RUN: llc -mtriple=mips64-elf -mcpu=i6400 < %s | \
; RUN: FileCheck %s --check-prefix=MIPS64
; RUN: llc -mtriple=mips-elf -mcpu=i6400 < %s | \
; RUN: FileCheck %s --check-prefix=MIPS32
; RUN: llc -mtriple=mips64-elf -mcpu=i6400 < %s | \
; RUN: FileCheck %s --check-prefix=MIPS64
; RUN: llc -mtriple=mips64-elf -mcpu=i6400 -mattr=-msa < %s | \
; RUN: FileCheck %s --check-prefix=NO-DSLA

define i32 @llvm_mips_lsa_test(i32 %a, i32 %b) nounwind {
entry:
%0 = tail call i32 @llvm.mips.lsa(i32 %a, i32 %b, i32 2)
ret i32 %0
}

declare i32 @llvm.mips.lsa(i32, i32, i32) nounwind

; MIPS32: llvm_mips_lsa_test:
; MIPS32: lsa {{\$[0-9]+}}, $5, $4, 2
; MIPS32: .size llvm_mips_lsa_test

define i32 @lsa_test(i32 %a, i32 %b) nounwind {
entry:
%0 = shl i32 %b, 2
%1 = add i32 %a, %0
ret i32 %1
}

; MIPS32: lsa_test:
; MIPS32: lsa {{\$[0-9]+}}, $5, $4, 2
; MIPS32: .size lsa_test

define i64 @llvm_mips_dlsa_test(i64 %a, i64 %b) nounwind {
entry:
%0 = tail call i64 @llvm.mips.dlsa(i64 %a, i64 %b, i32 2)
ret i64 %0
}

declare i64 @llvm.mips.dlsa(i64, i64, i32) nounwind

; MIPS64: llvm_mips_dlsa_test:
; MIPS64: dlsa {{\$[0-9]+}}, $5, $4, 2
; MIPS64: .size llvm_mips_dlsa_test
; NO-DSLA-NOT: dlsa {{\$[0-9]+}}, $5, $4, 2
define i64 @dlsa_test(i64 %a, i64 %b) nounwind {
entry:
%0 = shl i64 %b, 2
%1 = add i64 %a, %0
ret i64 %1
}

; MIPS64: dlsa_test:
; MIPS64: dlsa {{\$[0-9]+}}, $5, $4, 2
; MIPS64: .size dlsa_test
; NO-DSLA-NOT: dlsa {{\$[0-9]+}}, $5, $4, 2
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