Reland "[SelectionDAG] Introducing a new ISD::POISON SDNode to represent the poison value in the IR."

llvm/include/llvm/CodeGen/ISDOpcodes.h

@@ -217,6 +217,9 @@ enum NodeType {
   /// UNDEF - An undefined node.
   UNDEF,
 
+  /// POISON - A poison node.
+  POISON,
+
   /// FREEZE - FREEZE(VAL) returns an arbitrary value if VAL is UNDEF (or
   /// is evaluated to UNDEF), or returns VAL otherwise. Note that each
   /// read of UNDEF can yield different value, but FREEZE(UNDEF) cannot.

llvm/include/llvm/CodeGen/SelectionDAG.h

@@ -1130,6 +1130,9 @@ class SelectionDAG {
     return getNode(ISD::UNDEF, SDLoc(), VT);
   }
 
+  /// Return a POISON node. POISON does not have a useful SDLoc.
+  SDValue getPOISON(EVT VT) { return getNode(ISD::POISON, SDLoc(), VT); }
+
   /// Return a node that represents the runtime scaling 'MulImm * RuntimeVL'.
   SDValue getVScale(const SDLoc &DL, EVT VT, APInt MulImm,
                     bool ConstantFold = true);

llvm/include/llvm/CodeGen/SelectionDAGNodes.h

@@ -692,8 +692,10 @@ END_TWO_BYTE_PACK()
   /// \<target\>ISD namespace).
   bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
 
-  /// Return true if the type of the node type undefined.
-  bool isUndef() const { return NodeType == ISD::UNDEF; }
+  /// Returns true if the node type is UNDEF or POISON.
+  bool isUndef() const {
+    return NodeType == ISD::UNDEF || NodeType == ISD::POISON;
+  }
 
   /// Test if this node is a memory intrinsic (with valid pointer information).
   bool isMemIntrinsic() const { return SDNodeBits.IsMemIntrinsic; }

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -16304,7 +16304,8 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
   // Finally, recreate the node, it's operands were updated to use
   // frozen operands, so we just need to use it's "original" operands.
   SmallVector<SDValue> Ops(N0->ops());
-  // Special-handle ISD::UNDEF, each single one of them can be it's own thing.
+  // TODO: ISD::UNDEF and ISD::POISON should get separate handling, but best
+  // leave for a future patch.
   for (SDValue &Op : Ops) {
     if (Op.isUndef())
       Op = DAG.getFreeze(Op);

llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

@@ -986,6 +986,19 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
   TargetLowering::LegalizeAction Action = TargetLowering::Legal;
   bool SimpleFinishLegalizing = true;
   switch (Node->getOpcode()) {
+  // TODO: Currently, POISON is being lowered to UNDEF here. However, there is
+  // an open concern that this transformation may not be ideal, as targets
+  // should ideally handle POISON directly. Changing this behavior would require
+  // adding support for POISON in TableGen, which is a large change.
+  // Additionally, many existing test cases rely on the current behavior (e.g.,
+  // llvm/test/CodeGen/PowerPC/vec_shuffle.ll). A broader discussion and
+  // incremental changes might be needed to properly
+  // support POISON without breaking existing targets and tests.
+  case ISD::POISON: {
+    SDValue UndefNode = DAG.getUNDEF(Node->getValueType(0));
+    ReplaceNode(Node, UndefNode.getNode());
+    break;
+  }
   case ISD::INTRINSIC_W_CHAIN:
   case ISD::INTRINSIC_WO_CHAIN:
   case ISD::INTRINSIC_VOID:
@@ -3169,6 +3182,7 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
     for (unsigned i = 0; i < Node->getNumValues(); i++)
       Results.push_back(Node->getOperand(i));
     break;
+  case ISD::POISON:
   case ISD::UNDEF: {
     EVT VT = Node->getValueType(0);
     if (VT.isInteger())

llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

@@ -165,6 +165,7 @@ void DAGTypeLegalizer::SoftenFloatResult(SDNode *N, unsigned ResNo) {
     case ISD::STRICT_UINT_TO_FP:
     case ISD::SINT_TO_FP:
     case ISD::UINT_TO_FP:  R = SoftenFloatRes_XINT_TO_FP(N); break;
+    case ISD::POISON:
     case ISD::UNDEF:       R = SoftenFloatRes_UNDEF(N); break;
     case ISD::VAARG:       R = SoftenFloatRes_VAARG(N); break;
     case ISD::VECREDUCE_FADD:
@@ -1501,6 +1502,7 @@ void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) {
     report_fatal_error("Do not know how to expand the result of this "
                        "operator!");
     // clang-format off
+  case ISD::POISON:
   case ISD::UNDEF:        SplitRes_UNDEF(N, Lo, Hi); break;
   case ISD::SELECT:       SplitRes_Select(N, Lo, Hi); break;
   case ISD::SELECT_CC:    SplitRes_SELECT_CC(N, Lo, Hi); break;
@@ -2845,6 +2847,7 @@ void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) {
 
     case ISD::SINT_TO_FP:
     case ISD::UINT_TO_FP: R = PromoteFloatRes_XINT_TO_FP(N); break;
+    case ISD::POISON:
     case ISD::UNDEF:      R = PromoteFloatRes_UNDEF(N); break;
     case ISD::ATOMIC_SWAP: R = BitcastToInt_ATOMIC_SWAP(N); break;
     case ISD::VECREDUCE_FADD:
@@ -3318,6 +3321,7 @@ void DAGTypeLegalizer::SoftPromoteHalfResult(SDNode *N, unsigned ResNo) {
   case ISD::STRICT_UINT_TO_FP:
   case ISD::SINT_TO_FP:
   case ISD::UINT_TO_FP:  R = SoftPromoteHalfRes_XINT_TO_FP(N); break;
+  case ISD::POISON:
   case ISD::UNDEF:       R = SoftPromoteHalfRes_UNDEF(N); break;
   case ISD::ATOMIC_SWAP: R = BitcastToInt_ATOMIC_SWAP(N); break;
   case ISD::VECREDUCE_FADD:

llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

@@ -118,6 +118,7 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
   case ISD::VP_SRL:      Res = PromoteIntRes_SRL(N); break;
   case ISD::VP_TRUNCATE:
   case ISD::TRUNCATE:    Res = PromoteIntRes_TRUNCATE(N); break;
+  case ISD::POISON:
   case ISD::UNDEF:       Res = PromoteIntRes_UNDEF(N); break;
   case ISD::VAARG:       Res = PromoteIntRes_VAARG(N); break;
   case ISD::VSCALE:      Res = PromoteIntRes_VSCALE(N); break;
@@ -2914,6 +2915,7 @@ void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
   case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
   case ISD::SELECT:       SplitRes_Select(N, Lo, Hi); break;
   case ISD::SELECT_CC:    SplitRes_SELECT_CC(N, Lo, Hi); break;
+  case ISD::POISON:
   case ISD::UNDEF:        SplitRes_UNDEF(N, Lo, Hi); break;
   case ISD::FREEZE:       SplitRes_FREEZE(N, Lo, Hi); break;
   case ISD::SETCC:        ExpandIntRes_SETCC(N, Lo, Hi); break;

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

@@ -71,6 +71,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
   case ISD::SELECT:            R = ScalarizeVecRes_SELECT(N); break;
   case ISD::SELECT_CC:         R = ScalarizeVecRes_SELECT_CC(N); break;
   case ISD::SETCC:             R = ScalarizeVecRes_SETCC(N); break;
+  case ISD::POISON:
   case ISD::UNDEF:             R = ScalarizeVecRes_UNDEF(N); break;
   case ISD::VECTOR_SHUFFLE:    R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
   case ISD::IS_FPCLASS:        R = ScalarizeVecRes_IS_FPCLASS(N); break;
@@ -1137,6 +1138,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
   case ISD::VP_MERGE:
   case ISD::VP_SELECT:    SplitRes_Select(N, Lo, Hi); break;
   case ISD::SELECT_CC:    SplitRes_SELECT_CC(N, Lo, Hi); break;
+  case ISD::POISON:
   case ISD::UNDEF:        SplitRes_UNDEF(N, Lo, Hi); break;
   case ISD::BITCAST:           SplitVecRes_BITCAST(N, Lo, Hi); break;
   case ISD::BUILD_VECTOR:      SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
@@ -4592,6 +4594,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) {
   case ISD::SELECT_CC:         Res = WidenVecRes_SELECT_CC(N); break;
   case ISD::VP_SETCC:
   case ISD::SETCC:             Res = WidenVecRes_SETCC(N); break;
+  case ISD::POISON:
   case ISD::UNDEF:             Res = WidenVecRes_UNDEF(N); break;
   case ISD::VECTOR_SHUFFLE:
     Res = WidenVecRes_VECTOR_SHUFFLE(cast<ShuffleVectorSDNode>(N));

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

@@ -5387,6 +5387,9 @@ bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison(SDValue Op,
   case ISD::CopyFromReg:
     return true;
 
+  case ISD::POISON:
+    return false;
+
   case ISD::UNDEF:
     return PoisonOnly;
 

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

@@ -1817,7 +1817,7 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
       return DAG.getConstantFP(*CFP, getCurSDLoc(), VT);
 
     if (isa<UndefValue>(C) && !V->getType()->isAggregateType())
-      return DAG.getUNDEF(VT);
+      return isa<PoisonValue>(C) ? DAG.getPOISON(VT) : DAG.getUNDEF(VT);
 
     if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
       visit(CE->getOpcode(), *CE);

llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

@@ -189,6 +189,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
   case ISD::CopyToReg:                  return "CopyToReg";
   case ISD::CopyFromReg:                return "CopyFromReg";
   case ISD::UNDEF:                      return "undef";
+  case ISD::POISON:                     return "poison";
   case ISD::VSCALE:                     return "vscale";
   case ISD::MERGE_VALUES:               return "merge_values";
   case ISD::INLINEASM:                  return "inlineasm";

llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

@@ -3279,6 +3279,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
   case ISD::WRITE_REGISTER:
     Select_WRITE_REGISTER(NodeToMatch);
     return;
+  case ISD::POISON:
   case ISD::UNDEF:
     Select_UNDEF(NodeToMatch);
     return;

llvm/test/CodeGen/AArch64/vector-insert-dag-combines.ll

@@ -12,15 +12,15 @@ target triple = "aarch64-unknown-linux-gnu"
 ; CHECK:   t0: ch,glue = EntryToken
 ; CHECK:         t2: v8i8,ch = CopyFromReg t0, Register:v8i8 %0
 ; CHECK:       t4: v4i8 = extract_subvector t2, Constant:i64<0>
-; CHECK:     t6: v16i8 = insert_subvector undef:v16i8, t4, Constant:i64<0>
+; CHECK:     t6: v16i8 = insert_subvector poison:v16i8, t4, Constant:i64<0>
 ; CHECK:   t8: ch,glue = CopyToReg t0, Register:v16i8 $q0, t6
 ; CHECK:   t9: ch = AArch64ISD::RET_GLUE t8, Register:v16i8 $q0, t8:1
 
 ; CHECK: Optimized lowered selection DAG: %bb.0 'insert_small_fixed_into_big_fixed:'
 ; CHECK: SelectionDAG has 9 nodes:
 ; CHECK:   t0: ch,glue = EntryToken
 ; CHECK:       t2: v8i8,ch = CopyFromReg t0, Register:v8i8 %0
-; CHECK:     t10: v16i8 = insert_subvector undef:v16i8, t2, Constant:i64<0>
+; CHECK:     t10: v16i8 = insert_subvector poison:v16i8, t2, Constant:i64<0>
 ; CHECK:   t8: ch,glue = CopyToReg t0, Register:v16i8 $q0, t10
 ; CHECK:   t9: ch = AArch64ISD::RET_GLUE t8, Register:v16i8 $q0, t8:1
 
@@ -35,15 +35,15 @@ define <16 x i8> @insert_small_fixed_into_big_fixed(<8 x i8> %a) #0 {
 ; CHECK:   t0: ch,glue = EntryToken
 ; CHECK:         t2: v8i8,ch = CopyFromReg t0, Register:v8i8 %0
 ; CHECK:       t4: v4i8 = extract_subvector t2, Constant:i64<0>
-; CHECK:     t6: nxv16i8 = insert_subvector undef:nxv16i8, t4, Constant:i64<0>
+; CHECK:     t6: nxv16i8 = insert_subvector poison:nxv16i8, t4, Constant:i64<0>
 ; CHECK:   t8: ch,glue = CopyToReg t0, Register:nxv16i8 $z0, t6
 ; CHECK:   t9: ch = AArch64ISD::RET_GLUE t8, Register:nxv16i8 $z0, t8:1
 
 ; CHECK: Optimized lowered selection DAG: %bb.0 'insert_small_fixed_into_big_scalable:'
 ; CHECK: SelectionDAG has 9 nodes:
 ; CHECK:   t0: ch,glue = EntryToken
 ; CHECK:       t2: v8i8,ch = CopyFromReg t0, Register:v8i8 %0
-; CHECK:     t10: nxv16i8 = insert_subvector undef:nxv16i8, t2, Constant:i64<0>
+; CHECK:     t10: nxv16i8 = insert_subvector poison:nxv16i8, t2, Constant:i64<0>
 ; CHECK:   t8: ch,glue = CopyToReg t0, Register:nxv16i8 $z0, t10
 ; CHECK:   t9: ch = AArch64ISD::RET_GLUE t8, Register:nxv16i8 $z0, t8:1
 
@@ -59,7 +59,7 @@ define <vscale x 16 x i8> @insert_small_fixed_into_big_scalable(<8 x i8> %a) #0
 ; CHECK:           t2: nxv8i16,ch = CopyFromReg t0, Register:nxv8i16 %0
 ; CHECK:         t3: nxv8i8 = truncate t2
 ; CHECK:       t5: v4i8 = extract_subvector t3, Constant:i64<0>
-; CHECK:     t7: v16i8 = insert_subvector undef:v16i8, t5, Constant:i64<0>
+; CHECK:     t7: v16i8 = insert_subvector poison:v16i8, t5, Constant:i64<0>
 ; CHECK:   t9: ch,glue = CopyToReg t0, Register:v16i8 $q0, t7
 ; CHECK:   t10: ch = AArch64ISD::RET_GLUE t9, Register:v16i8 $q0, t9:1
 
@@ -69,7 +69,7 @@ define <vscale x 16 x i8> @insert_small_fixed_into_big_scalable(<8 x i8> %a) #0
 ; CHECK:           t2: nxv8i16,ch = CopyFromReg t0, Register:nxv8i16 %0
 ; CHECK:         t3: nxv8i8 = truncate t2
 ; CHECK:       t5: v4i8 = extract_subvector t3, Constant:i64<0>
-; CHECK:     t7: v16i8 = insert_subvector undef:v16i8, t5, Constant:i64<0>
+; CHECK:     t7: v16i8 = insert_subvector poison:v16i8, t5, Constant:i64<0>
 ; CHECK:   t9: ch,glue = CopyToReg t0, Register:v16i8 $q0, t7
 ; CHECK:   t10: ch = AArch64ISD::RET_GLUE t9, Register:v16i8 $q0, t9:1
 
@@ -86,7 +86,7 @@ define <16 x i8> @insert_small_scalable_into_big_fixed(<vscale x 8 x i8> %a) #0
 ; CHECK:           t2: nxv8i16,ch = CopyFromReg t0, Register:nxv8i16 %0
 ; CHECK:         t3: nxv8i8 = truncate t2
 ; CHECK:       t5: v4i8 = extract_subvector t3, Constant:i64<0>
-; CHECK:     t7: nxv16i8 = insert_subvector undef:nxv16i8, t5, Constant:i64<0>
+; CHECK:     t7: nxv16i8 = insert_subvector poison:nxv16i8, t5, Constant:i64<0>
 ; CHECK:   t9: ch,glue = CopyToReg t0, Register:nxv16i8 $z0, t7
 ; CHECK:   t10: ch = AArch64ISD::RET_GLUE t9, Register:nxv16i8 $z0, t9:1
 
@@ -95,7 +95,7 @@ define <16 x i8> @insert_small_scalable_into_big_fixed(<vscale x 8 x i8> %a) #0
 ; CHECK:   t0: ch,glue = EntryToken
 ; CHECK:         t2: nxv8i16,ch = CopyFromReg t0, Register:nxv8i16 %0
 ; CHECK:       t3: nxv8i8 = truncate t2
-; CHECK:     t11: nxv16i8 = insert_subvector undef:nxv16i8, t3, Constant:i64<0>
+; CHECK:     t11: nxv16i8 = insert_subvector poison:nxv16i8, t3, Constant:i64<0>
 ; CHECK:   t9: ch,glue = CopyToReg t0, Register:nxv16i8 $z0, t11
 ; CHECK:   t10: ch = AArch64ISD::RET_GLUE t9, Register:nxv16i8 $z0, t9:1
 
@@ -111,7 +111,7 @@ define <vscale x 16 x i8> @insert_small_scalable_into_big_scalable_1(<vscale x 8
 ; CHECK:           t2: nxv8i16,ch = CopyFromReg t0, Register:nxv8i16 %0
 ; CHECK:         t3: nxv8i8 = truncate t2
 ; CHECK:       t5: nxv4i8 = extract_subvector t3, Constant:i64<0>
-; CHECK:     t7: nxv16i8 = insert_subvector undef:nxv16i8, t5, Constant:i64<0>
+; CHECK:     t7: nxv16i8 = insert_subvector poison:nxv16i8, t5, Constant:i64<0>
 ; CHECK:   t9: ch,glue = CopyToReg t0, Register:nxv16i8 $z0, t7
 ; CHECK:   t10: ch = AArch64ISD::RET_GLUE t9, Register:nxv16i8 $z0, t9:1
 
@@ -120,7 +120,7 @@ define <vscale x 16 x i8> @insert_small_scalable_into_big_scalable_1(<vscale x 8
 ; CHECK:   t0: ch,glue = EntryToken
 ; CHECK:         t2: nxv8i16,ch = CopyFromReg t0, Register:nxv8i16 %0
 ; CHECK:       t3: nxv8i8 = truncate t2
-; CHECK:     t11: nxv16i8 = insert_subvector undef:nxv16i8, t3, Constant:i64<0>
+; CHECK:     t11: nxv16i8 = insert_subvector poison:nxv16i8, t3, Constant:i64<0>
 ; CHECK:   t9: ch,glue = CopyToReg t0, Register:nxv16i8 $z0, t11
 ; CHECK:   t10: ch = AArch64ISD::RET_GLUE t9, Register:nxv16i8 $z0, t9:1
 
@@ -135,7 +135,7 @@ define <vscale x 16 x i8> @insert_small_scalable_into_big_scalable_2(<vscale x 8
 ; CHECK:   t0: ch,glue = EntryToken
 ; CHECK:         t2: v16i8,ch = CopyFromReg t0, Register:v16i8 %0
 ; CHECK:       t4: v4i8 = extract_subvector t2, Constant:i64<0>
-; CHECK:     t6: v8i8 = insert_subvector undef:v8i8, t4, Constant:i64<0>
+; CHECK:     t6: v8i8 = insert_subvector poison:v8i8, t4, Constant:i64<0>
 ; CHECK:   t8: ch,glue = CopyToReg t0, Register:v8i8 $d0, t6
 ; CHECK:   t9: ch = AArch64ISD::RET_GLUE t8, Register:v8i8 $d0, t8:1
 
@@ -158,7 +158,7 @@ define <8 x i8> @extract_small_fixed_from_big_fixed(<16 x i8> %a) #0 {
 ; CHECK:   t0: ch,glue = EntryToken
 ; CHECK:           t2: v16i8,ch = CopyFromReg t0, Register:v16i8 %0
 ; CHECK:         t4: v4i8 = extract_subvector t2, Constant:i64<0>
-; CHECK:       t6: nxv8i8 = insert_subvector undef:nxv8i8, t4, Constant:i64<0>
+; CHECK:       t6: nxv8i8 = insert_subvector poison:nxv8i8, t4, Constant:i64<0>
 ; CHECK:     t7: nxv8i16 = any_extend t6
 ; CHECK:   t9: ch,glue = CopyToReg t0, Register:nxv8i16 $z0, t7
 ; CHECK:   t10: ch = AArch64ISD::RET_GLUE t9, Register:nxv8i16 $z0, t9:1
@@ -168,7 +168,7 @@ define <8 x i8> @extract_small_fixed_from_big_fixed(<16 x i8> %a) #0 {
 ; CHECK:   t0: ch,glue = EntryToken
 ; CHECK:           t2: v16i8,ch = CopyFromReg t0, Register:v16i8 %0
 ; CHECK:         t4: v4i8 = extract_subvector t2, Constant:i64<0>
-; CHECK:       t6: nxv8i8 = insert_subvector undef:nxv8i8, t4, Constant:i64<0>
+; CHECK:       t6: nxv8i8 = insert_subvector poison:nxv8i8, t4, Constant:i64<0>
 ; CHECK:     t7: nxv8i16 = any_extend t6
 ; CHECK:   t9: ch,glue = CopyToReg t0, Register:nxv8i16 $z0, t7
 ; CHECK:   t10: ch = AArch64ISD::RET_GLUE t9, Register:nxv8i16 $z0, t9:1
@@ -185,7 +185,7 @@ define <vscale x 8 x i8> @extract_small_scalable_from_big_fixed(<16 x i8> %a) #0
 ; CHECK:   t0: ch,glue = EntryToken
 ; CHECK:         t2: nxv16i8,ch = CopyFromReg t0, Register:nxv16i8 %0
 ; CHECK:       t4: v4i8 = extract_subvector t2, Constant:i64<0>
-; CHECK:     t6: v8i8 = insert_subvector undef:v8i8, t4, Constant:i64<0>
+; CHECK:     t6: v8i8 = insert_subvector poison:v8i8, t4, Constant:i64<0>
 ; CHECK:   t8: ch,glue = CopyToReg t0, Register:v8i8 $d0, t6
 ; CHECK:   t9: ch = AArch64ISD::RET_GLUE t8, Register:v8i8 $d0, t8:1
 
@@ -208,7 +208,7 @@ define <8 x i8> @extract_small_fixed_from_big_scalable(<vscale x 16 x i8> %a) #0
 ; CHECK:   t0: ch,glue = EntryToken
 ; CHECK:           t2: nxv16i8,ch = CopyFromReg t0, Register:nxv16i8 %0
 ; CHECK:         t4: v4i8 = extract_subvector t2, Constant:i64<0>
-; CHECK:       t6: nxv8i8 = insert_subvector undef:nxv8i8, t4, Constant:i64<0>
+; CHECK:       t6: nxv8i8 = insert_subvector poison:nxv8i8, t4, Constant:i64<0>
 ; CHECK:     t7: nxv8i16 = any_extend t6
 ; CHECK:   t9: ch,glue = CopyToReg t0, Register:nxv8i16 $z0, t7
 ; CHECK:   t10: ch = AArch64ISD::RET_GLUE t9, Register:nxv8i16 $z0, t9:1
@@ -233,7 +233,7 @@ define <vscale x 8 x i8> @extract_small_scalable_from_big_scalable_1(<vscale x 1
 ; CHECK:   t0: ch,glue = EntryToken
 ; CHECK:           t2: nxv16i8,ch = CopyFromReg t0, Register:nxv16i8 %0
 ; CHECK:         t4: nxv4i8 = extract_subvector t2, Constant:i64<0>
-; CHECK:       t6: nxv8i8 = insert_subvector undef:nxv8i8, t4, Constant:i64<0>
+; CHECK:       t6: nxv8i8 = insert_subvector poison:nxv8i8, t4, Constant:i64<0>
 ; CHECK:     t7: nxv8i16 = any_extend t6
 ; CHECK:   t9: ch,glue = CopyToReg t0, Register:nxv8i16 $z0, t7
 ; CHECK:   t10: ch = AArch64ISD::RET_GLUE t9, Register:nxv8i16 $z0, t9:1
@@ -258,7 +258,7 @@ define <vscale x 8 x i8> @extract_small_scalable_from_big_scalable_2(<vscale x 1
 ; CHECK:   t0: ch,glue = EntryToken
 ; CHECK:         t2: nxv16i8,ch = CopyFromReg t0, Register:nxv16i8 %0
 ; CHECK:       t4: v4i8 = extract_subvector t2, Constant:i64<0>
-; CHECK:     t6: v16i8 = insert_subvector undef:v16i8, t4, Constant:i64<0>
+; CHECK:     t6: v16i8 = insert_subvector poison:v16i8, t4, Constant:i64<0>
 ; CHECK:   t8: ch,glue = CopyToReg t0, Register:v16i8 $q0, t6
 ; CHECK:   t9: ch = AArch64ISD::RET_GLUE t8, Register:v16i8 $q0, t8:1
 
@@ -285,15 +285,15 @@ define <16 x i8> @extract_fixed_from_scalable(<vscale x 16 x i8> %a) #0 {
 ; CHECK:   t0: ch,glue = EntryToken
 ; CHECK:         t2: v16i8,ch = CopyFromReg t0, Register:v16i8 %0
 ; CHECK:       t4: v4i8 = extract_subvector t2, Constant:i64<0>
-; CHECK:     t6: nxv16i8 = insert_subvector undef:nxv16i8, t4, Constant:i64<0>
+; CHECK:     t6: nxv16i8 = insert_subvector poison:nxv16i8, t4, Constant:i64<0>
 ; CHECK:   t8: ch,glue = CopyToReg t0, Register:nxv16i8 $z0, t6
 ; CHECK:   t9: ch = AArch64ISD::RET_GLUE t8, Register:nxv16i8 $z0, t8:1
 
 ; CHECK: Optimized lowered selection DAG: %bb.0 'insert_fixed_into_scalable:'
 ; CHECK: SelectionDAG has 9 nodes:
 ; CHECK:   t0: ch,glue = EntryToken
 ; CHECK:       t2: v16i8,ch = CopyFromReg t0, Register:v16i8 %0
-; CHECK:     t10: nxv16i8 = insert_subvector undef:nxv16i8, t2, Constant:i64<0>
+; CHECK:     t10: nxv16i8 = insert_subvector poison:nxv16i8, t2, Constant:i64<0>
 ; CHECK:   t8: ch,glue = CopyToReg t0, Register:nxv16i8 $z0, t10
 ; CHECK:   t9: ch = AArch64ISD::RET_GLUE t8, Register:nxv16i8 $z0, t8:1
 

llvm/test/CodeGen/PowerPC/poison-legalization.ll

@@ -0,0 +1,11 @@
+; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu  | FileCheck %s
+
+define void @ExpandFloat(ptr %p1 )  {
+; CHECK:      stfd 0, 8(3) 
+; CHECK-NEXT: stfd 0, 0(3)
+; CHECK-NEXT: blr
+entry:
+   store volatile ppc_fp128 poison, ptr %p1
+   ret void
+}
+

llvm/test/CodeGen/RISCV/poison-legalization.ll

@@ -0,0 +1,24 @@
+; RUN: llc < %s -mtriple=riscv32  | FileCheck %s
+
+define void @SoftenFloat(ptr %p1)  {
+; CHECK-LABEL: SoftenFloat:
+; CHECK:       # %bb.0:                                # %entry
+; CHECK-NEXT:     sw      a0, 4(a0)
+; CHECK-NEXT:     sw      a0, 0(a0)
+; CHECK-NEXT:     ret
+
+entry:
+  store volatile double poison, ptr %p1
+  ret void
+}
+
+define void @PromoteHalf(ptr %p1 )  {
+; CHECK-LABEL: PromoteHalf:
+; CHECK:       # %bb.0:                                # %entry
+; CHECK-NEXT:     sh      a0, 0(a0)
+; CHECK-NEXT:     ret
+entry:
+   store volatile half poison, ptr %p1
+   ret void
+}
+