[SystemZ] Add a SystemZ specific pre-RA scheduling strategy.

llvm/include/llvm/CodeGen/MachineScheduler.h

@@ -1095,6 +1095,7 @@ class GenericSchedulerBase : public MachineSchedStrategy {
     NoCand,
     Only1,
     PhysReg,
+    LivenessReduce,
     RegExcess,
     RegCritical,
     Stall,
@@ -1223,12 +1224,13 @@ class GenericSchedulerBase : public MachineSchedStrategy {
   void traceCandidate(const SchedCandidate &Cand);
 #endif
 
-private:
+protected:
   bool shouldReduceLatency(const CandPolicy &Policy, SchedBoundary &CurrZone,
                            bool ComputeRemLatency, unsigned &RemLatency) const;
 };
 
 // Utility functions used by heuristics in tryCandidate().
+LLVM_ABI unsigned computeRemLatency(SchedBoundary &CurrZone);
 LLVM_ABI bool tryLess(int TryVal, int CandVal,
                       GenericSchedulerBase::SchedCandidate &TryCand,
                       GenericSchedulerBase::SchedCandidate &Cand,

llvm/include/llvm/CodeGen/RegisterPressure.h

@@ -413,6 +413,8 @@ class RegPressureTracker {
   /// tracker before the first call to advance/recede.
   LLVM_ABI void addLiveRegs(ArrayRef<VRegMaskOrUnit> Regs);
 
+  bool isRegLive(Register Reg) const { return LiveRegs.contains(Reg).any(); }
+
   /// Get the MI position corresponding to this register pressure.
   MachineBasicBlock::const_iterator getPos() const { return CurrPos; }
 

llvm/lib/CodeGen/MachineScheduler.cpp

@@ -95,6 +95,8 @@ STATISTIC(NumOnly1PreRA,
           "Number of scheduling units chosen for Only1 heuristic pre-RA");
 STATISTIC(NumPhysRegPreRA,
           "Number of scheduling units chosen for PhysReg heuristic pre-RA");
+STATISTIC(NumLiveReducePreRA,
+          "Number of scheduling units chosen for LiveReduce heuristic pre-RA");
 STATISTIC(NumRegExcessPreRA,
           "Number of scheduling units chosen for RegExcess heuristic pre-RA");
 STATISTIC(NumRegCriticalPreRA,
@@ -140,6 +142,8 @@ STATISTIC(NumOnly1PostRA,
           "Number of scheduling units chosen for Only1 heuristic post-RA");
 STATISTIC(NumPhysRegPostRA,
           "Number of scheduling units chosen for PhysReg heuristic post-RA");
+STATISTIC(NumLiveReducePostRA,
+          "Number of scheduling units chosen for LiveReduce heuristic post-RA");
 STATISTIC(NumRegExcessPostRA,
           "Number of scheduling units chosen for RegExcess heuristic post-RA");
 STATISTIC(
@@ -3263,31 +3267,6 @@ initResourceDelta(const ScheduleDAGMI *DAG,
   }
 }
 
-/// Compute remaining latency. We need this both to determine whether the
-/// overall schedule has become latency-limited and whether the instructions
-/// outside this zone are resource or latency limited.
-///
-/// The "dependent" latency is updated incrementally during scheduling as the
-/// max height/depth of scheduled nodes minus the cycles since it was
-/// scheduled:
-///   DLat = max (N.depth - (CurrCycle - N.ReadyCycle) for N in Zone
-///
-/// The "independent" latency is the max ready queue depth:
-///   ILat = max N.depth for N in Available|Pending
-///
-/// RemainingLatency is the greater of independent and dependent latency.
-///
-/// These computations are expensive, especially in DAGs with many edges, so
-/// only do them if necessary.
-static unsigned computeRemLatency(SchedBoundary &CurrZone) {
-  unsigned RemLatency = CurrZone.getDependentLatency();
-  RemLatency = std::max(RemLatency,
-                        CurrZone.findMaxLatency(CurrZone.Available.elements()));
-  RemLatency = std::max(RemLatency,
-                        CurrZone.findMaxLatency(CurrZone.Pending.elements()));
-  return RemLatency;
-}
-
 /// Returns true if the current cycle plus remaning latency is greater than
 /// the critical path in the scheduling region.
 bool GenericSchedulerBase::shouldReduceLatency(const CandPolicy &Policy,
@@ -3373,6 +3352,7 @@ const char *GenericSchedulerBase::getReasonStr(
   case NoCand:         return "NOCAND    ";
   case Only1:          return "ONLY1     ";
   case PhysReg:        return "PHYS-REG  ";
+  case LivenessReduce: return "LIVE-REDUC";
   case RegExcess:      return "REG-EXCESS";
   case RegCritical:    return "REG-CRIT  ";
   case Stall:          return "STALL     ";
@@ -3446,6 +3426,31 @@ void GenericSchedulerBase::traceCandidate(const SchedCandidate &Cand) {
 #endif
 
 namespace llvm {
+/// Compute remaining latency. We need this both to determine whether the
+/// overall schedule has become latency-limited and whether the instructions
+/// outside this zone are resource or latency limited.
+///
+/// The "dependent" latency is updated incrementally during scheduling as the
+/// max height/depth of scheduled nodes minus the cycles since it was
+/// scheduled:
+///   DLat = max (N.depth - (CurrCycle - N.ReadyCycle) for N in Zone
+///
+/// The "independent" latency is the max ready queue depth:
+///   ILat = max N.depth for N in Available|Pending
+///
+/// RemainingLatency is the greater of independent and dependent latency.
+///
+/// These computations are expensive, especially in DAGs with many edges, so
+/// only do them if necessary.
+unsigned computeRemLatency(SchedBoundary &CurrZone) {
+  unsigned RemLatency = CurrZone.getDependentLatency();
+  RemLatency = std::max(RemLatency,
+                        CurrZone.findMaxLatency(CurrZone.Available.elements()));
+  RemLatency = std::max(RemLatency,
+                        CurrZone.findMaxLatency(CurrZone.Pending.elements()));
+  return RemLatency;
+}
+
 /// Return true if this heuristic determines order.
 /// TODO: Consider refactor return type of these functions as integer or enum,
 /// as we may need to differentiate whether TryCand is better than Cand.
@@ -3537,6 +3542,9 @@ static void tracePick(GenericSchedulerBase::CandReason Reason, bool IsTop,
     case GenericScheduler::PhysReg:
       NumPhysRegPostRA++;
       return;
+    case GenericScheduler::LivenessReduce:
+      NumLiveReducePostRA++;
+      return;
     case GenericScheduler::RegExcess:
       NumRegExcessPostRA++;
       return;
@@ -3596,6 +3604,9 @@ static void tracePick(GenericSchedulerBase::CandReason Reason, bool IsTop,
     case GenericScheduler::PhysReg:
       NumPhysRegPreRA++;
       return;
+    case GenericScheduler::LivenessReduce:
+      NumLiveReducePreRA++;
+      return;
     case GenericScheduler::RegExcess:
       NumRegExcessPreRA++;
       return;