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3 changes: 2 additions & 1 deletion llvm/lib/Target/RISCV/RISCVProcessors.td
Original file line number Diff line number Diff line change
Expand Up @@ -86,7 +86,8 @@ class RISCVTuneProcessorModel<string n,
list<SubtargetFeature> f = []>
: ProcessorModel<n, m, f,tunef>;

defvar GenericTuneFeatures = [TuneOptimizedNF2SegmentLoadStore];
defvar GenericTuneFeatures = [TuneOptimizedNF2SegmentLoadStore,
TuneNoDefaultUnroll];

def GENERIC_RV32 : RISCVProcessorModel<"generic-rv32",
NoSchedModel,
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4 changes: 4 additions & 0 deletions llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2652,6 +2652,10 @@ void RISCVTTIImpl::getUnrollingPreferences(
// taken cost of the backedge.
if (Cost < 12)
UP.Force = true;

// Set a lower runtime unrolling count for in-order models.
if (!ST->getSchedModel().isOutOfOrder())
UP.DefaultUnrollRuntimeCount = 4;
}

void RISCVTTIImpl::getPeelingPreferences(Loop *L, ScalarEvolution &SE,
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