Skip to content

[AMDGPU][MC] test update with script for vinterp asm test #135681

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Apr 15, 2025
Merged

[AMDGPU][MC] test update with script for vinterp asm test #135681

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
14 changes: 1 addition & 13 deletions llvm/test/MC/AMDGPU/vinterp.s
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5
// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --unique --version 5
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -show-encoding %s | FileCheck -check-prefix=GCN %s
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 -show-encoding %s | FileCheck -check-prefix=GCN %s

Expand Down Expand Up @@ -98,9 +98,6 @@ v_interp_p10_f16_f32 v0, v1.l, v2, v3.l wait_exp:1
v_interp_p10_f16_f32 v0, v1.l, v2, v3.l wait_exp:7
// GCN: v_interp_p10_f16_f32 v0, v1.l, v2, v3.l wait_exp:7 ; encoding: [0x00,0x07,0x02,0xcd,0x01,0x05,0x0e,0x04]

v_interp_p10_f16_f32 v0, v1.l, v2, v3.l
Copy link
Contributor

@shiltian shiltian Apr 14, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Are they removed because they are duplicated?

Copy link
Contributor Author

@broxigarchen broxigarchen Apr 15, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Yes

// GCN: v_interp_p10_f16_f32 v0, v1.l, v2, v3.l wait_exp:0 ; encoding: [0x00,0x00,0x02,0xcd,0x01,0x05,0x0e,0x04]

v_interp_p10_f16_f32 v0, v1.h, v2, v3.l
// GCN: v_interp_p10_f16_f32 v0, v1.h, v2, v3.l wait_exp:0 ; encoding: [0x00,0x08,0x02,0xcd,0x01,0x05,0x0e,0x04]

Expand Down Expand Up @@ -137,9 +134,6 @@ v_interp_p2_f16_f32 v0.l, v1.l, v2, v3 wait_exp:1
v_interp_p2_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7
// GCN: v_interp_p2_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7 ; encoding: [0x00,0x07,0x03,0xcd,0x01,0x05,0x0e,0x04]

v_interp_p2_f16_f32 v0.l, v1.l, v2, v3
// GCN: v_interp_p2_f16_f32 v0.l, v1.l, v2, v3 wait_exp:0 ; encoding: [0x00,0x00,0x03,0xcd,0x01,0x05,0x0e,0x04]

v_interp_p2_f16_f32 v0.l, v1.h, v2, v3
// GCN: v_interp_p2_f16_f32 v0.l, v1.h, v2, v3 wait_exp:0 ; encoding: [0x00,0x08,0x03,0xcd,0x01,0x05,0x0e,0x04]

Expand Down Expand Up @@ -179,9 +173,6 @@ v_interp_p10_rtz_f16_f32 v0, v1.l, v2, v3.l wait_exp:1
v_interp_p10_rtz_f16_f32 v0, v1.l, v2, v3.l wait_exp:7
// GCN: v_interp_p10_rtz_f16_f32 v0, v1.l, v2, v3.l wait_exp:7 ; encoding: [0x00,0x07,0x04,0xcd,0x01,0x05,0x0e,0x04]

v_interp_p10_rtz_f16_f32 v0, v1.l, v2, v3.l
// GCN: v_interp_p10_rtz_f16_f32 v0, v1.l, v2, v3.l wait_exp:0 ; encoding: [0x00,0x00,0x04,0xcd,0x01,0x05,0x0e,0x04]

v_interp_p10_rtz_f16_f32 v0, v1.h, v2, v3.l
// GCN: v_interp_p10_rtz_f16_f32 v0, v1.h, v2, v3.l wait_exp:0 ; encoding: [0x00,0x08,0x04,0xcd,0x01,0x05,0x0e,0x04]

Expand Down Expand Up @@ -218,9 +209,6 @@ v_interp_p2_rtz_f16_f32 v0.l, v1.l, v2, v3 wait_exp:1
v_interp_p2_rtz_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7
// GCN: v_interp_p2_rtz_f16_f32 v0.l, v1.l, v2, v3 wait_exp:7 ; encoding: [0x00,0x07,0x05,0xcd,0x01,0x05,0x0e,0x04]

v_interp_p2_rtz_f16_f32 v0.l, v1.l, v2, v3
// GCN: v_interp_p2_rtz_f16_f32 v0.l, v1.l, v2, v3 wait_exp:0 ; encoding: [0x00,0x00,0x05,0xcd,0x01,0x05,0x0e,0x04]

v_interp_p2_rtz_f16_f32 v0.l, v1.h, v2, v3
// GCN: v_interp_p2_rtz_f16_f32 v0.l, v1.h, v2, v3 wait_exp:0 ; encoding: [0x00,0x08,0x05,0xcd,0x01,0x05,0x0e,0x04]

Expand Down
Loading